soc/intel/baytrail: Fix Kconfig for mrc.bin inclusion
It used the sandybridge systemagent binary and mentioned that in the help text which is simply wrong and won't work. This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by default. Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27140 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -67,22 +67,20 @@ config SMM_RESERVED_SIZE
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default 0x100000
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default 0x100000
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config HAVE_MRC
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config HAVE_MRC
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bool "Add a Memory Reference Code binary"
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bool "Add a System Agent binary"
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default y
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help
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help
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Select this option to add a blob containing
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Select this option to add a System Agent binary to
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memory reference code.
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the resulting coreboot image.
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Note: Without this binary coreboot will not work
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Note: Without this binary coreboot will not work
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if HAVE_MRC
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config MRC_FILE
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config MRC_FILE
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string "Intel memory refeference code path and filename"
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string "Intel System Agent path and filename"
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default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
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depends on HAVE_MRC
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default "mrc.bin"
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help
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help
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The path and filename of the file to use as System Agent
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The path and filename of the file to use as System Agent
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binary. Note that this points to the sandybridge binary file
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binary.
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which is will not work, but it serves its purpose to do builds.
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config MRC_BIN_ADDRESS
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config MRC_BIN_ADDRESS
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hex
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hex
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@ -92,8 +90,6 @@ config MRC_RMT
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bool "Enable MRC RMT training + debug prints"
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bool "Enable MRC RMT training + debug prints"
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default n
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default n
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endif # HAVE_MRC
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# Cache As RAM region layout:
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# Cache As RAM region layout:
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#
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#
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
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