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soc/intel/baytrail: Fix Kconfig for mrc.bin inclusion 

It used the sandybridge systemagent binary and mentioned that in the
help text which is simply wrong and won't work.

This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by
default.

Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27140
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-06-17 21:36:22 +02:00 committed by Patrick Georgi
parent a8a9f34e9b
commit abe62be81d
1 changed files with 8 additions and 12 deletions
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20
src/soc/intel/baytrail/Kconfig
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@ -67,22 +67,20 @@ config SMM_RESERVED_SIZE
default 0x100000
config HAVE_MRC
bool "Add a Memory Reference Code binary"
default y
bool "Add a System Agent binary"
help
Select this option to add a blob containing
memory reference code.
Select this option to add a System Agent binary to
the resulting coreboot image.
Note: Without this binary coreboot will not work
if HAVE_MRC
config MRC_FILE
string "Intel memory refeference code path and filename"
default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
string "Intel System Agent path and filename"
depends on HAVE_MRC
default "mrc.bin"
help
The path and filename of the file to use as System Agent
binary. Note that this points to the sandybridge binary file
which is will not work, but it serves its purpose to do builds.
binary.
config MRC_BIN_ADDRESS
hex
@ -92,8 +90,6 @@ config MRC_RMT
bool "Enable MRC RMT training + debug prints"
default n
endif # HAVE_MRC
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE