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Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` 

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Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3220
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Paul Menzel 2013-05-08 17:08:55 +02:00 committed by Ronald G. Minnich
parent 59158b2fb0
commit abe6847cd2
3 changed files with 6 additions and 8 deletions
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5
src/northbridge/intel/gm45/delay.c
View File

@ -24,7 +24,7 @@
#include "delay.h"
/**
* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
* Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
*/
static void _udelay(const u32 us, const u32 numerator, const int total)
{
@ -62,8 +62,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total)
msr = rdmsr(0x198);
divisor = (msr.hi >> 8) & 0x1f;
/* CPU clock is always a quarter. */
d = ((fsb * divisor) / numerator) / 4;
d = ((fsb * divisor) / numerator) / 4; /* CPU clock is always a quarter. */
multiply_to_tsc(&tscd, us, d);

3
src/northbridge/intel/i945/udelay.c
View File

@ -24,7 +24,7 @@
#include <cpu/intel/speedstep.h>
/**
* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
* Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
*/
void udelay(u32 us)
@ -79,5 +79,4 @@ void udelay(u32 us)
tsc = rdtsc();
} while ((tsc.hi < tsc1.hi)
|| ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
}