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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -6,8 +6,15 @@ uses PCIC0_CFGADDR
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uses PCIC0_CFGDATA
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uses UART0_IO_BASE
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##
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## Set PCI registers
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##
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option PCIC0_CFGADDR=0xeec00000
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option PCIC0_CFGDATA=0xeec00004
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##
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## Set UART base address
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##
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option UART0_IO_BASE=0xef600300
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arch ppc end
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@ -14,6 +14,7 @@ uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_CHIP_CONFIGURE
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uses NO_POST
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BASE
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uses CONFIG_IDE_STREAM
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uses IDE_BOOT_DRIVE
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uses IDE_SWAB IDE_OFFSET
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@ -46,6 +47,7 @@ option NO_POST=1
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## Enable serial console
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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option TTYS0_BASE=0xfe000000
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## Boot linux from IDE
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option CONFIG_IDE_STREAM=1
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