GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Revert "soc/intel/xeon_sp: Improve performance efficiencies" 

This reverts commit d51449d017.

Reason for revert: Causing compilation issue as below

src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa':
src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization
discards 'const' qualifier from pointer target type
[-Werror=discarded-qualifiers]
    &hob->PlatformData.IIO_resource[socket];
    ^
Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-09-28 13:44:15 +00:00
parent 9e7c99dcae
commit ac17fad84e
1 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/soc/intel/xeon_sp/cpx/acpi.c
View File

@ -605,16 +605,16 @@ static int get_stack_for_port(int port)
* in the context of ATSR subtable, it adds ATSR subtable when it is first called.
*/
static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current,
int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg,
int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg,
bool is_atsr, bool *first)
{
if (get_stack_for_port(port) != stack)
return 0;
const uint32_t bus = iio_resource->StackRes[stack].BusBase;
const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device;
const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function;
const uint32_t bus = iio_resource.StackRes[stack].BusBase;
const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device;
const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function;
const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func),
PCI_VENDOR_ID);
@ -703,8 +703,8 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket,
// Add PCIe Ports
if (socket != 0 || stack != CSTACK) {
const IIO_RESOURCE_INSTANCE *iio_resource =
&hob->PlatformData.IIO_resource[socket];
IIO_RESOURCE_INSTANCE iio_resource =
hob->PlatformData.IIO_resource[socket];
for (int p = PORT_0; p < MAX_PORTS; ++p)
current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack,
iio_resource, pcie_seg, false, NULL);
@ -748,12 +748,12 @@ static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob)
uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment;
unsigned long tmp = current;
bool first = true;
const IIO_RESOURCE_INSTANCE *iio_resource =
&hob->PlatformData.IIO_resource[socket];
IIO_RESOURCE_INSTANCE iio_resource =
hob->PlatformData.IIO_resource[socket];
for (int stack = 0; stack <= PSTACK2; ++stack) {
uint32_t bus = iio_resource->StackRes[stack].BusBase;
uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress;
uint32_t bus = iio_resource.StackRes[stack].BusBase;
uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress;
if (!vtd_base)
continue;
uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW));
@ -821,10 +821,10 @@ static unsigned long acpi_create_rhsa(unsigned long current)
assert(hob != NULL && hob_size != 0);
for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
IIO_RESOURCE_INSTANCE *iio_resource =
&hob->PlatformData.IIO_resource[socket];
IIO_RESOURCE_INSTANCE iio_resource =
hob->PlatformData.IIO_resource[socket];
for (int stack = 0; stack <= PSTACK2; ++stack) {
uint32_t vtd_base = iio_resource->StackRes[stack].VtdBarAddress;
uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress;
if (!vtd_base)
continue;