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amd/southbridge/lpc: SPI BAR has fixed size/location 

The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.

Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Dave Frodin 2014-06-05 14:30:22 -06:00
parent 61f902d4a7
commit ac1b875b55
8 changed files with 41 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/southbridge/amd/agesa/hudson/hudson.h
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2010 Advanced Micro Devices, Inc. * Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -50,7 +51,9 @@
#define REV_HUDSON_A11 0x11 #define REV_HUDSON_A11 0x11
#define REV_HUDSON_A12 0x12 #define REV_HUDSON_A12 0x12
#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#define SPI_ROM_ENABLE 0x02
#define SPI_BASE_ADDRESS 0xFEC10000
#ifndef __SMM__ #ifndef __SMM__

11
src/southbridge/amd/agesa/hudson/lpc.c
View File

@ -87,8 +87,6 @@ static void hudson_lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
pci_get_resource(dev, 0xA0); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0; res->base = 0;
@ -102,6 +100,9 @@ static void hudson_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED; IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); /* IOAPIC */ res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR; res->base = IO_APIC_ADDR;
res->size = 0x00001000; res->size = 0x00001000;
@ -115,12 +116,10 @@ static void hudson_lpc_set_resources(struct device *dev)
struct resource *res; struct resource *res;
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); res = find_resource(dev, 2);
res->base |= PCI_COMMAND_MEMORY; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev); pci_dev_set_resources(dev);
} }
/** /**

13
src/southbridge/amd/cimx/sb700/lpc.c
View File

@ -46,8 +46,6 @@ void lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0; res->base = 0;
@ -61,6 +59,9 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED; IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); res = new_resource(dev, 3);
res->base = IO_APIC_ADDR; res->base = IO_APIC_ADDR;
res->size = 0x00001000; res->size = 0x00001000;
@ -75,11 +76,13 @@ void lpc_set_resources(struct device *dev)
struct resource *res; struct resource *res;
printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
res = find_resource(dev, 2);
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev); pci_dev_set_resources(dev);
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS);
pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
} }

4
src/southbridge/amd/cimx/sb700/lpc.h
View File

@ -21,7 +21,9 @@
#define _SB700_LPC_H_ #define _SB700_LPC_H_
#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ #define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#define SPI_ROM_ENABLE 0x02
#define SPI_BASE_ADDRESS 0xFEC10000
void lpc_read_resources(device_t dev); void lpc_read_resources(device_t dev);
void lpc_set_resources(device_t dev); void lpc_set_resources(device_t dev);

10
src/southbridge/amd/cimx/sb800/lpc.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2011 Advanced Micro Devices, Inc. * Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -33,8 +34,6 @@ void lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
pci_get_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0; res->base = 0;
@ -48,6 +47,9 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED; IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); res = new_resource(dev, 3);
res->base = IO_APIC_ADDR; res->base = IO_APIC_ADDR;
res->size = 0x00001000; res->size = 0x00001000;
@ -64,8 +66,8 @@ void lpc_set_resources(struct device *dev)
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n");
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); res = find_resource(dev, 2);
res->base |= PCI_COMMAND_MEMORY; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev); pci_dev_set_resources(dev);

5
src/southbridge/amd/cimx/sb800/lpc.h
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2011 Advanced Micro Devices, Inc. * Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -20,7 +21,9 @@
#ifndef _SB800_LPC_H_ #ifndef _SB800_LPC_H_
#define _SB800_LPC_H_ #define _SB800_LPC_H_
#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 /* SPI ROM base address */ #define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#define SPI_ROM_ENABLE 0x02
#define SPI_BASE_ADDRESS 0xFEC10000
void lpc_read_resources(device_t dev); void lpc_read_resources(device_t dev);
void lpc_set_resources(device_t dev); void lpc_set_resources(device_t dev);

13
src/southbridge/amd/cimx/sb900/lpc.c
View File

@ -31,8 +31,6 @@ void lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0; res->base = 0;
@ -46,6 +44,9 @@ void lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED; IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); res = new_resource(dev, 3);
res->base = IO_APIC_ADDR; res->base = IO_APIC_ADDR;
res->size = 0x00001000; res->size = 0x00001000;
@ -60,11 +61,13 @@ void lpc_set_resources(struct device *dev)
struct resource *res; struct resource *res;
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n"); printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n");
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
res = find_resource(dev, 2);
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev); pci_dev_set_resources(dev);
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS);
pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n"); printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n");
} }

5
src/southbridge/amd/cimx/sb900/lpc.h
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@ -20,8 +20,9 @@
#ifndef _SB900_LPC_H_ #ifndef _SB900_LPC_H_
#define _SB900_LPC_H_ #define _SB900_LPC_H_
#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ #define SPI_ROM_ENABLE 0x02
#define SPI_BASE_ADDRESS 0xFEC10000
void lpc_read_resources(device_t dev); void lpc_read_resources(device_t dev);
void lpc_set_resources(device_t dev); void lpc_set_resources(device_t dev);