broadwell: Clean up `mainboard_post_raminit`

Make it optional and change its signature.

Change-Id: I4b5f3fb08e8954514ebf39e72c95aa62d66856d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

src/mainboard/google/auron/romstage.c

@@ -14,7 +14,3 @@ void mainboard_pre_raminit(struct romstage_params *rp)
 	mainboard_fill_spd_data(&rp->pei_data);
 
 }
-
-__weak void mainboard_post_raminit(struct romstage_params *rp)
-{
-}

src/mainboard/google/auron/variants/gandof/variant.c

@@ -24,8 +24,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return len;
 }
 
-void mainboard_post_raminit(struct romstage_params *rp)
+void mainboard_post_raminit(const int s3resume)
 {
-	if (rp->power_state->prev_sleep_state != ACPI_S3)
+	if (!s3resume)
 		google_chromeec_kbbacklight(75);
 }

src/mainboard/google/auron/variants/lulu/variant.c

@@ -34,8 +34,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return len;
 }
 
-void mainboard_post_raminit(struct romstage_params *rp)
+void mainboard_post_raminit(const int s3resume)
 {
-	if (rp->power_state->prev_sleep_state != ACPI_S3)
+	if (!s3resume)
 		google_chromeec_kbbacklight(75);
 }

src/mainboard/google/auron/variants/samus/variant.c

@@ -21,9 +21,9 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return 0;
 }
 
-void mainboard_post_raminit(struct romstage_params *rp)
+void mainboard_post_raminit(const int s3resume)
 {
-	if (rp->power_state->prev_sleep_state != ACPI_S3)
+	if (!s3resume)
 		google_chromeec_kbbacklight(100);
 
 	printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());

src/mainboard/google/jecht/romstage.c

@@ -18,7 +18,7 @@ void mainboard_pre_raminit(struct romstage_params *rp)
 	mainboard_fill_spd_data(&rp->pei_data);
 }
 
-void mainboard_post_raminit(struct romstage_params *rp)
+void mainboard_post_raminit(const int s3resume)
 {
 	if (CONFIG(CHROMEOS))
 		init_bootmode_straps();

src/mainboard/intel/wtm2/romstage.c

@@ -11,7 +11,3 @@ void mainboard_pre_raminit(struct romstage_params *rp)
 	/* Fill out PEI DATA */
 	mainboard_fill_pei_data(&rp->pei_data);
 }
-
-void mainboard_post_raminit(struct romstage_params *rp)
-{
-}

src/mainboard/purism/librem_bdw/romstage.c

@@ -9,7 +9,3 @@ void mainboard_pre_raminit(struct romstage_params *rp)
 	/* Fill out PEI DATA */
 	mainboard_fill_pei_data(&rp->pei_data);
 }
-
-void mainboard_post_raminit(struct romstage_params *rp)
-{
-}

src/soc/intel/broadwell/include/soc/romstage.h

@@ -12,7 +12,7 @@ struct romstage_params {
 };
 
 void mainboard_pre_raminit(struct romstage_params *params);
-void mainboard_post_raminit(struct romstage_params *params);
+void mainboard_post_raminit(const int s3resume);
 
 void raminit(struct pei_data *pei_data);
 

src/soc/intel/broadwell/romstage.c

@@ -14,6 +14,10 @@
 #include <stdint.h>
 #include <timestamp.h>
 
+__weak void mainboard_post_raminit(const int s3resume)
+{
+}
+
 /* Entry from cpu/intel/car/romstage.c. */
 void mainboard_romstage_entry(void)
 {
@@ -64,5 +68,5 @@ void mainboard_romstage_entry(void)
 
 	romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3);
 
-	mainboard_post_raminit(&rp);
+	mainboard_post_raminit(rp.power_state->prev_sleep_state == ACPI_S3);
 }