mb/*/romstage: Don't lock ETR3 CF9GR in early romstage

Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.

Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/gigabyte/ga-b75m-d3h/romstage.c

@@ -153,7 +153,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 
 	/* Initialize SuperIO */
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/gigabyte/ga-b75m-d3v/romstage.c

@@ -85,7 +85,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 
 	/* Initialize SuperIO */
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/lenovo/l520/romstage.c

@@ -31,7 +31,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
 }
 
 void rcba_config(void)

src/mainboard/lenovo/s230u/romstage.c

@@ -43,7 +43,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);
 
 	/* Memory map KB9012 EC registers */
 	pci_write_config32(

src/mainboard/lenovo/t420/romstage.c

@@ -33,7 +33,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 void rcba_config(void)

src/mainboard/lenovo/t420s/romstage.c

@@ -36,7 +36,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 void rcba_config(void)

src/mainboard/lenovo/t430s/romstage.c

@@ -36,7 +36,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 void rcba_config(void)

src/mainboard/lenovo/t520/romstage.c

@@ -50,8 +50,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac,
-			   0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 void rcba_config(void)

src/mainboard/lenovo/t530/romstage.c

@@ -37,8 +37,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac,
-			   0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 void rcba_config(void)

src/mainboard/lenovo/x1_carbon_gen1/romstage.c

@@ -51,8 +51,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac,
-			   0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/lenovo/x220/romstage.c

@@ -47,8 +47,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac,
-			   0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 void rcba_config(void)

src/mainboard/lenovo/x230/romstage.c

@@ -50,8 +50,7 @@ void pch_enable_lpc(void)
 
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-	pci_write_config32(PCH_LPC_DEV, 0xac,
-			   0x80010000);
+	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
 void rcba_config(void)