From ac350f82cd4dfab20a6fb49e5dea536ae448e054 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 15 May 2018 16:59:06 +0200 Subject: [PATCH] sb/intel/fsp_i89xx: Get rid of device_t Use of device_t is discouraged unless necessary. Change-Id: I89f9fe94c1e3e5c2b183572d7f603d016d0f0e1c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26249 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/fsp_i89xx/early_smbus.c | 2 +- src/southbridge/intel/fsp_i89xx/early_usb.c | 2 +- src/southbridge/intel/fsp_i89xx/lpc.c | 20 +++++++++---------- src/southbridge/intel/fsp_i89xx/me.c | 14 ++++++------- src/southbridge/intel/fsp_i89xx/me_8.x.c | 14 ++++++------- src/southbridge/intel/fsp_i89xx/pch.c | 10 +++++----- src/southbridge/intel/fsp_i89xx/pch.h | 2 +- src/southbridge/intel/fsp_i89xx/romstage.c | 2 +- src/southbridge/intel/fsp_i89xx/sata.c | 5 +++-- src/southbridge/intel/fsp_i89xx/smihandler.c | 2 +- src/southbridge/intel/fsp_i89xx/watchdog.c | 2 +- 11 files changed, 38 insertions(+), 37 deletions(-) diff --git a/src/southbridge/intel/fsp_i89xx/early_smbus.c b/src/southbridge/intel/fsp_i89xx/early_smbus.c index 1451179915..97d4381a55 100644 --- a/src/southbridge/intel/fsp_i89xx/early_smbus.c +++ b/src/southbridge/intel/fsp_i89xx/early_smbus.c @@ -24,7 +24,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/fsp_i89xx/early_usb.c b/src/southbridge/intel/fsp_i89xx/early_usb.c index 744af01fa0..29ab9811c2 100644 --- a/src/southbridge/intel/fsp_i89xx/early_usb.c +++ b/src/southbridge/intel/fsp_i89xx/early_usb.c @@ -31,7 +31,7 @@ */ void enable_usb_bar(void) { - device_t usb0 = PCH_EHCI1_DEV; + pci_devfn_t usb0 = PCH_EHCI1_DEV; u32 cmd; /* USB Controller 0 */ diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 3a17701f8e..f584f36a76 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -112,9 +112,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -154,7 +154,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -183,7 +183,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, GPIO_ROUT, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -415,7 +415,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -476,18 +476,18 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -498,7 +498,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(device_t dev) +static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -524,7 +524,7 @@ static void southbridge_inject_dsdt(device_t dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c index 4b5a4b3ce5..5dfd70df87 100644 --- a/src/southbridge/intel/fsp_i89xx/me.c +++ b/src/southbridge/intel/fsp_i89xx/me.c @@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -509,7 +509,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -576,7 +576,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -606,7 +606,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -653,14 +653,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -702,7 +702,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c index b77cad2aad..aec6cd68ec 100644 --- a/src/southbridge/intel/fsp_i89xx/me_8.x.c +++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c @@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -490,7 +490,7 @@ void intel_me8_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -564,7 +564,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -594,7 +594,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -641,14 +641,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; @@ -692,7 +692,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_i89xx/pch.c b/src/southbridge/intel/fsp_i89xx/pch.c index d17aa5bdd8..626791ca1e 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.c +++ b/src/southbridge/intel/fsp_i89xx/pch.c @@ -122,9 +122,9 @@ static inline int iobp_poll(void) /* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) +static int pch_pcie_check_set_enabled(struct device *dev) { - device_t port; + struct device *port; int port_func; int dev_func = PCI_FUNC(dev->path.pci.devfn); @@ -171,7 +171,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_devicetree_update(void) { - device_t dev; + struct device *dev; /* Update the function numbers in the static devicetree */ for (dev = all_devices; dev; dev = dev->next) { @@ -200,7 +200,7 @@ static void pch_pcie_devicetree_update(void) } /* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_fsp_i89xx_config *config = dev->chip_info; u32 reg32; @@ -307,7 +307,7 @@ static void pch_pcie_enable(device_t dev) } } -void pch_enable(device_t dev) +void pch_enable(struct device *dev) { u32 reg32; diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index a1d2a4b303..3382cbd881 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -64,7 +64,7 @@ void intel_pch_finalize_smm(void); int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); -void pch_enable(device_t dev); +void pch_enable(struct device *dev); #if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index a08972024f..afe00bd6aa 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -50,7 +50,7 @@ static inline void reset_system(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/southbridge/intel/fsp_i89xx/sata.c b/src/southbridge/intel/fsp_i89xx/sata.c index 810847a861..bbd21e0859 100644 --- a/src/southbridge/intel/fsp_i89xx/sata.c +++ b/src/southbridge/intel/fsp_i89xx/sata.c @@ -78,11 +78,12 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index 8a6506b77a..3658a82d4c 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -242,7 +242,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/southbridge/intel/fsp_i89xx/watchdog.c b/src/southbridge/intel/fsp_i89xx/watchdog.c index 74f69b032b..9a867e413a 100644 --- a/src/southbridge/intel/fsp_i89xx/watchdog.c +++ b/src/southbridge/intel/fsp_i89xx/watchdog.c @@ -28,7 +28,7 @@ // void watchdog_off(void) { - device_t dev; + struct device *dev; unsigned long value, base; /* Turn off the ICH7 watchdog. */