nb/intel/gm45/gm45.h: Clean up cosmetics
Align groups of definitions, reflow long lines and adjust whitespace. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I2969274c6b50f56994e45ada5d016504addfc13e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Angel Pons
parent
9c2d15ff7f
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ac4e4b423f
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@ -10,9 +10,9 @@
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#include <stdint.h>
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typedef enum {
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FSB_CLOCK_1067MHz = 0,
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FSB_CLOCK_800MHz = 1,
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FSB_CLOCK_667MHz = 2,
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FSB_CLOCK_1067MHz = 0,
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FSB_CLOCK_800MHz = 1,
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FSB_CLOCK_667MHz = 2,
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} fsb_clock_t;
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typedef enum { /* Steppings below B1 were pre-production,
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@ -43,12 +43,12 @@ typedef enum {
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} gmch_gfx_t;
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typedef enum {
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MEM_CLOCK_533MHz = 0,
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MEM_CLOCK_400MHz = 1,
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MEM_CLOCK_333MHz = 2,
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MEM_CLOCK_1067MT = 0,
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MEM_CLOCK_800MT = 1,
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MEM_CLOCK_667MT = 2,
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MEM_CLOCK_533MHz = 0,
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MEM_CLOCK_400MHz = 1,
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MEM_CLOCK_333MHz = 2,
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MEM_CLOCK_1067MT = 0,
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MEM_CLOCK_800MT = 1,
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MEM_CLOCK_667MT = 2,
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} mem_clock_t;
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typedef enum {
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@ -132,6 +132,7 @@ typedef struct {
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int gs45_low_power_mode; /* low power mode of GMCH_GS45 */
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int sff; /* small form factor option (soldered down DIMM) */
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} sysinfo_t;
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#define TOTAL_CHANNELS 2
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#define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
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#define CHANNEL_IS_CARDF(dimms, idx) (dimms[idx].card_type == 0xf)
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@ -167,51 +168,50 @@ enum {
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/* Offsets of read/write training results in CMOS.
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They will be restored upon S3 resumes. */
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#define CMOS_READ_TRAINING 0x80 /* 16 bytes */
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#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes
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(could be reduced to 10 bytes) */
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#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */
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#define DEFAULT_MCHBAR 0xfed14000
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#define DEFAULT_DMIBAR 0xfed18000
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#define DEFAULT_EPBAR 0xfed19000
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#define IOMMU_BASE1 0xfed90000
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#define IOMMU_BASE2 0xfed91000
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#define IOMMU_BASE3 0xfed92000
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#define IOMMU_BASE4 0xfed93000
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#define IOMMU_BASE1 0xfed90000
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#define IOMMU_BASE2 0xfed91000
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#define IOMMU_BASE3 0xfed92000
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#define IOMMU_BASE4 0xfed93000
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/*
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* D0:F0
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*/
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#define D0F0_EPBAR_LO 0x40
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#define D0F0_EPBAR_HI 0x44
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#define D0F0_MCHBAR_LO 0x48
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#define D0F0_MCHBAR_HI 0x4c
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#define D0F0_GGC 0x52
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#define D0F0_DEVEN 0x54
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#define D0F0_PCIEXBAR_LO 0x60
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#define D0F0_PCIEXBAR_HI 0x64
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#define D0F0_DMIBAR_LO 0x68
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#define D0F0_DMIBAR_HI 0x6c
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#define D0F0_PMBASE 0x78
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#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/
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#define D0F0_REMAPBASE 0x98
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#define D0F0_REMAPLIMIT 0x9a
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#define D0F0_SMRAM 0x9d
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#define D0F0_ESMRAMC 0x9e
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#define D0F0_TOM 0xa0
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#define D0F0_TOUUD 0xa2
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#define D0F0_TOLUD 0xb0
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#define D0F0_SKPD 0xdc /* Scratchpad Data */
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#define D0F0_CAPID0 0xe0
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#define D0F0_EPBAR_LO 0x40
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#define D0F0_EPBAR_HI 0x44
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#define D0F0_MCHBAR_LO 0x48
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#define D0F0_MCHBAR_HI 0x4c
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#define D0F0_GGC 0x52
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#define D0F0_DEVEN 0x54
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#define D0F0_PCIEXBAR_LO 0x60
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#define D0F0_PCIEXBAR_HI 0x64
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#define D0F0_DMIBAR_LO 0x68
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#define D0F0_DMIBAR_HI 0x6c
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#define D0F0_PMBASE 0x78
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#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */
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#define D0F0_REMAPBASE 0x98
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#define D0F0_REMAPLIMIT 0x9a
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#define D0F0_SMRAM 0x9d
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#define D0F0_ESMRAMC 0x9e
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#define D0F0_TOM 0xa0
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#define D0F0_TOUUD 0xa2
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#define D0F0_TOLUD 0xb0
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#define D0F0_SKPD 0xdc /* Scratchpad Data */
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#define D0F0_CAPID0 0xe0
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/*
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* D1:F0 PEG
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*/
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#define PEG_CAP 0xa2
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#define SLOTCAP 0xb4
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#define PEGLC 0xec
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#define D1F0_VCCAP 0x104
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#define D1F0_VC0RCTL 0x114
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#define PEG_CAP 0xa2
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#define SLOTCAP 0xb4
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#define PEGLC 0xec
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#define D1F0_VCCAP 0x104
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#define D1F0_VC0RCTL 0x114
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/*
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* Graphics frequencies
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@ -231,7 +231,7 @@ enum {
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* MCHBAR
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*/
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#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
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@ -286,7 +286,7 @@ enum {
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* Every two ranks share one register and must be programmed at the same time.
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* All registers (4 ranks per channel) have to be set.
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*/
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#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r/2) * 4))
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#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r / 2) * 4))
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#define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16)
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#define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r))
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#define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \
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@ -344,44 +344,45 @@ enum {
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/* Write Training registers. */
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#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4))
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#define CxGTEW(x) (0x1270+(x*0x100))
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#define CxGTC(x) (0x1274+(x*0x100))
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#define CxDTPEW(x) (0x1278+(x*0x100))
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#define CxDTAEW(x) (0x1280+(x*0x100))
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#define CxDTC(x) (0x1288+(x*0x100))
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#define CxGTEW(x) (0x1270 + (x * 0x100))
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#define CxGTC(x) (0x1274 + (x * 0x100))
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#define CxDTPEW(x) (0x1278 + (x * 0x100))
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#define CxDTAEW(x) (0x1280 + (x * 0x100))
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#define CxDTC(x) (0x1288 + (x * 0x100))
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/*
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* DMIBAR
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*/
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#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
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#define DMIVC0RCTL 0x14
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#define DMIVC1RCTL 0x20
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#define DMIVC1RSTS 0x26
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#define DMIESD 0x44
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#define DMILE1D 0x50
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#define DMILE1A 0x58
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#define DMILE2D 0x60
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#define DMILE2A 0x68
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#define DMIVC0RCTL 0x14
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#define DMIVC1RCTL 0x20
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#define DMIVC1RSTS 0x26
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#define DMIESD 0x44
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#define DMILE1D 0x50
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#define DMILE1A 0x58
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#define DMILE2D 0x60
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#define DMILE2A 0x68
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/*
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* EPBAR
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*/
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#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
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#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
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#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
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#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
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#define EPESD 0x44
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#define EPLE1D 0x50
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#define EPLE1A 0x58
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#define EPLE2D 0x60
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#define EPESD 0x44
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#define EPLE1D 0x50
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#define EPLE1A 0x58
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#define EPLE2D 0x60
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#ifndef __ACPI__
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void gm45_early_init(void);
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void gm45_early_reset(void);
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