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tegra124: use known-good drive for fast-train only 

A higher drive setting is used for fast link training, once the
link training succeeds, a known-good drive setting will be used
for the main stream transactions.
For full link training sequence, the sink devices may ask for a
preferred drive setting, thus this drive setting should be used
for the main stream transactions too.

BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.

Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219544
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>

(cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6
Reviewed-on: http://review.coreboot.org/9248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Neil Chen 2014-09-24 10:41:08 +08:00 committed by Aaron Durbin
parent 8c440a6bef
commit ac4fef8345
3 changed files with 29 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/nvidia/tegra124/dp.c
View File

@ -1254,6 +1254,9 @@ static int tegra_dp_do_link_training(struct tegra_dc_dp_data *dp,
printk(BIOS_ERR, "dp: full link training failed\n");
return ret;
}
} else {
/* set to a known-good drive setting if fast link succeeded */
tegra_dc_sor_set_voltage_swing(&dp->sor);
}
/* Everything goes well, double check the link config */

48
src/soc/nvidia/tegra124/sor.c
View File

@ -832,11 +832,34 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
0xf0, 0x0);
}
void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor)
{
u32 drive_current = 0;
u32 pre_emphasis = 0;
/* Set to a known-good pre-calibrated setting */
switch (sor->link_cfg->link_bw) {
case SOR_LINK_SPEED_G1_62:
case SOR_LINK_SPEED_G2_7:
drive_current = 0x13131313;
pre_emphasis = 0;
break;
case SOR_LINK_SPEED_G5_4:
printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n");
default:
printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n",
sor->link_cfg->link_bw);
return;
}
tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
drive_current);
tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis);
}
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor)
{
u32 pad_ctrl = 0;
u32 drive_current = 0;
u32 pre_emphasis = 0;
int err = 0;
switch (sor->link_cfg->lane_count) {
@ -873,27 +896,6 @@ void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor)
"Wait for lane power down failed: %d\n", err);
return;
}
/* Set to a known-good pre-calibrated setting */
switch (sor->link_cfg->link_bw) {
case SOR_LINK_SPEED_G1_62:
case SOR_LINK_SPEED_G2_7:
drive_current = 0x13131313;
pre_emphasis = 0;
break;
case SOR_LINK_SPEED_G5_4:
drive_current = 0x19191919;
pre_emphasis = 0x09090909;
break;
default:
printk(BIOS_ERR, "Invalid sor link bandwidth: %d\n",
sor->link_cfg->link_bw);
return;
}
tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
drive_current);
tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis);
}
void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor)

1
src/soc/nvidia/tegra124/sor.h
View File

@ -920,6 +920,7 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor);
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
const struct tegra_dc_dp_link_config *link_cfg);
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor);
void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor);
void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor);
void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor);
void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,