vc/amd/fsp/cezanne: add platform_descriptors.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Felix Held
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* These definitions are used to describe PCIe bifurcation and display physical
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* connector types connected to the SOC.
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*/
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#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H
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#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H
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#define NUM_DXIO_PHY_PARAMS 6
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#define NUM_DXIO_PORT_PARAMS 6
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/* Engine descriptor type */
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enum dxio_engine_type {
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UNUSED_ENGINE = 0x00, // Unused descriptor
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PCIE_ENGINE = 0x01, // PCIe port
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USB_ENGINE = 0x02, // USB port
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SATA_ENGINE = 0x03, // SATA
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DP_ENGINE = 0x08, // Digital Display
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ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe)
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MAX_ENGINE // Max engine type for boundary check.
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};
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/* PCIe link capability/speed */
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enum dxio_link_speed_cap {
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GEN_MAX = 0, // Maximum supported
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GEN1,
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GEN2,
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GEN3,
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GEN_INVALID // Max Gen for boundary check
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};
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/* Upstream Auto Speed Change Allowed */
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enum dxio_upstream_auto_speed_change {
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SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3
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SPDC_DISABLED,
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SPDC_ENABLED,
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SPDC_INVALID
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};
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/* SATA ChannelType initialization */
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enum dxio_sata_channel_type {
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SATA_CHANNEL_OTHER = 0, // Default Channel Type
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SATA_CHANNEL_SHORT, // Short Trace Channel Type
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SATA_CHANNEL_LONG // Long Trace Channel Type
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};
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/* CLKREQ for PCIe type descriptors */
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enum cpm_clk_req {
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CLK_DISABLE = 0x00,
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CLK_REQ0,
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CLK_REQ1,
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CLK_REQ2,
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CLK_REQ3,
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CLK_REQ4_GFX,
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CLK_REQ5,
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CLK_REQ6,
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CLK_ENABLE = 0xff,
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};
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/* PCIe link ASPM initialization */
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enum dxio_aspm_type {
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ASPM_DISABLED = 0, // Disabled
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ASPM_L0s, // PCIe L0s link state
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ASPM_L1, // PCIe L1 link state
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ASPM_L0sL1, // PCIe L0s & L1 link state
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ASPM_MAX // Not valid value, used to verify input
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};
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enum dxio_port_param_type {
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PP_DEVICE = 1,
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PP_FUNCTION,
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PP_PORT_PRESENT,
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PP_LINK_SPEED_CAP,
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PP_LINK_ASPM,
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PP_HOTPLUG_TYPE,
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PP_CLKREQ,
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PP_ASPM_L1_1,
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PP_ASPM_L1_2,
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PP_COMPLIANCE,
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PP_SAFE_MODE,
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PP_CHIPSET_LINK,
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PP_CLOCK_PM,
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PP_CHANNELTYPE,
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PP_TURN_OFF_UNUSED_LANES,
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PP_APIC_GROUPMAP,
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PP_APIC_SWIZZLE,
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PP_APIC_BRIDGEINT,
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PP_MASTER_PLL,
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PP_SLOT_NUM,
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PP_PHY_PARAM,
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PP_ESM,
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PP_CCIX,
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PP_GEN3_DS_TX_PRESET,
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PP_GEN3_DS_RX_PRESET_HINT,
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PP_GEN3_US_TX_PRESET,
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PP_GEN3_US_RX_PRESET_HINT,
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PP_GEN4_DS_TX_PRESET,
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PP_GEN4_US_TX_PRESET,
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PP_GEN3_FIXED_PRESET,
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PP_GEN4_FIXED_PRESET,
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PP_PSPP_DC,
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PP_PSPP_AC,
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PP_GEN2_DEEMPHASIS,
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PP_INVERT_POLARITY,
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PP_TARGET_LINK_SPEED,
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PP_GEN4_DLF_CAP_DISABLE,
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PP_GEN4_DLF_EXCHG_DISABLE
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};
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/* DDI Aux channel */
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enum ddi_aux_type {
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DDI_AUX1 = 0,
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DDI_AUX2,
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DDI_AUX3,
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DDI_AUX4,
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DDI_AUX5,
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DDI_AUX6,
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DDI_AUX_MAX // Not valid value, used to verify input
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};
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/* DDI Hdp Index */
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enum ddi_hdp_type {
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DDI_HDP1 = 0,
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DDI_HDP2,
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DDI_HDP3,
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DDI_HDP4,
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DDI_HDP5,
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DDI_HDP6,
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DDI_HDP_MAX // Not valid value, used to verify input
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};
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/* DDI display connector type */
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enum ddi_connector_type {
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DDI_DP = 0, // DP
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DDI_EDP, // eDP
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DDI_SINGLE_LINK_DVI, // Single Link DVI-D
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DDI_DUAL_LINK_DVI, // Dual Link DVI-D
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DDI_HDMI, // HDMI
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DDI_DP_TO_VGA, // DP-to-VGA
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DDI_DP_TO_LVDS, // DP-to-LVDS
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DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA
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DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I
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DDI_CRT, // CRT (VGA)
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DDI_LVDS, // LVDS
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DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init
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DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init
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DDI_AUTO_DETECT, // VBIOS auto detect connector type
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DDI_UNUSED_TYPE, // UnusedType
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DDI_MAX_CONNECTOR_TYPE // Not valid value, used to verify input
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};
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/* Cezanne DDI Descriptor: used for configuring display outputs */
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typedef struct __packed {
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uint8_t connector_type; // see ddi_connector_type
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uint8_t aux_index; // see ddi_aux_type
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uint8_t hdp_index; // see ddi_hdp_type
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uint8_t reserved;
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} fsp_ddi_descriptor;
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/*
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* Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines,
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* configure bifurcation and other settings. Beware that the lane numbers in
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* here are the logical and not the physical lane numbers!
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*
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* Cezanne DXIO logical lane to physical PCIe lane mapping:
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*
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* logical | FT6 | AM4
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* --------|------------|----------------------
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* [00:03] | GPP[00:03] | GPP[00:03]
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* [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03]
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* [08:11] | GPP[08:11] | GFX[15:12]
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* [12:15] | n/a | GFX[11:08]
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* [16:23] | GFX[00:07] | GFX[07:0]
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*
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* Different ports mustn't overlap or be assigned to the same lane(s). Within
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* ports with the same width the one with a higher start logical lane number
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* needs to be assigned to a higher PCIe root port number; ports of the same
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* size don't have to be assigned to consecutive PCIe root ports though.
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*
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* Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6
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* platform additionally supports mapping lanes 8 and 9 to a SATA controller.
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* On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet
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* controllers.
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*/
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typedef struct __packed {
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uint8_t engine_type; // See dxio_engine_type
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uint8_t start_logical_lane; // Start lane of the pci device
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uint8_t end_logical_lane; // End lane of the pci device
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uint8_t gpio_group_id; // GPIO number used as reset
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uint32_t port_present :1; // Should be TRUE if train link
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uint32_t reserved_3 :7;
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uint32_t device_number :5; // Desired root port device number
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uint32_t function_number :3; // Desired root port function number
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uint32_t link_speed_capability :2; // See dxio_link_speed_cap
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uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change
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uint32_t eq_preset :4; // Gen3 equalization preset
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uint32_t link_aspm :2; // See dxio_aspm_type
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uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1
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uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2
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uint32_t clk_req :4; // See cpm_clk_req
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uint8_t link_hotplug; // Currently unused by FSP
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uint8_t slot_power_limit; // Currently unused by FSP
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uint32_t slot_power_limit_scale :2; // Currently unused by FSP
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uint32_t reserved_4 :6;
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uint32_t link_compliance_mode :1; // Currently unused by FSP
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uint32_t link_safe_mode :1; // Currently unused by FSP
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uint32_t sb_link :1; // Currently unused by FSP
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uint32_t clk_pm_support :1; // Currently unused by FSP
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uint32_t channel_type :3; // See dxio_sata_channel_type
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uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present
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uint8_t reserved[4];
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uint8_t phy_params[NUM_DXIO_PHY_PARAMS*2];
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uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type
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} fsp_dxio_descriptor;
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#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */
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