Crank up CPU speed on Intel Core and Core2 CPUs

The CPUs start on their slowest speed, and were left that way by
coreboot. This change will speed up coreboot a bit, as well as
systems that don't change the clock for whatever reason.

Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/176
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2011-08-09 08:52:14 +02:00 committed by Patrick Georgi
parent 7981b940a6
commit ac624a638d
2 changed files with 28 additions and 0 deletions

View File

@ -30,6 +30,7 @@
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h> #include <cpu/intel/hyperthreading.h>
#include <cpu/intel/speedstep.h> #include <cpu/intel/speedstep.h>
#include <cpu/intel/acpi.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/name.h> #include <cpu/x86/name.h>
#include <usbdebug.h> #include <usbdebug.h>
@ -129,6 +130,19 @@ static void configure_misc(void)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr); wrmsr(IA32_MISC_ENABLE, msr);
// set maximum CPU speed
msr = rdmsr(IA32_PERF_STS);
int busratio_max=(msr.hi >> (40-32)) & 0x1f;
msr = rdmsr(IA32_PLATFORM_ID);
int vid_max=msr.lo & 0x3f;
msr.lo &= ~0xffff;
msr.lo |= busratio_max << 8;
msr.lo |= vid_max;
wrmsr(IA32_PERF_CTL, msr);
} }
#define PIC_SENS_CFG 0x1aa #define PIC_SENS_CFG 0x1aa

View File

@ -29,6 +29,7 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h> #include <cpu/intel/speedstep.h>
#include <cpu/intel/acpi.h>
#include <cpu/intel/hyperthreading.h> #include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/name.h> #include <cpu/x86/name.h>
@ -156,6 +157,19 @@ static void configure_misc(void)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr); wrmsr(IA32_MISC_ENABLE, msr);
// set maximum CPU speed
msr = rdmsr(IA32_PERF_STS);
int busratio_max=(msr.hi >> (40-32)) & 0x1f;
msr = rdmsr(IA32_PLATFORM_ID);
int vid_max=msr.lo & 0x3f;
msr.lo &= ~0xffff;
msr.lo |= busratio_max << 8;
msr.lo |= vid_max;
wrmsr(IA32_PERF_CTL, msr);
} }
#define PIC_SENS_CFG 0x1aa #define PIC_SENS_CFG 0x1aa