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vendorcode/amd/agesa: Fix variable length array declaration 

Definition of S_PSTATE only allowed PStateStruct[0], while it is
effectively used as a flexible array. Since sizeof(S_PSTATE) is
reduced here by sizeof(S_PSTATE_VALUES), we have to account for
that when calculating PStateLevelingSizeOfBytes.

In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference.

GCC 7.2.0 warns about an out of bounds array subscript.

```
    CC         libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain':
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds]
             PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~

[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html

Change-Id: If9598a951c6b882432689b677a956c44650c7083
Found-by: gcc (Debian 7.2.0-2) 7.2.0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21297
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Paul Menzel 2017-08-31 06:47:38 +02:00 committed by Patrick Georgi
parent 25c7e322e8
commit ac63b415ed
5 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
View File

@ -78,7 +78,7 @@ typedef struct {
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states
IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node

12
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
View File

@ -248,9 +248,10 @@ PStateGatherMain (
//Calculate next node buffer address
//
PStateBufferPtr->SocketNumber = (UINT8) BscSocket;
PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES));
PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue;
PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES));
PStateStrucPtr->SizeOfBytes += (MaxState + 1) * sizeof (S_PSTATE_VALUES);
PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes);
CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader);
//
//Get CPU P-States and fill the PStateBufferPtr for each node(BSC)
@ -266,9 +267,10 @@ PStateGatherMain (
//
//Calculate next node buffer address
//
PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue;
PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES));
PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes;
PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes);
}
}
}

2
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
View File

@ -79,7 +79,7 @@ typedef struct {
IN OUT UINT8 HtcPstateLimit; ///< Htc limit
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node

2
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
View File

@ -78,7 +78,7 @@ typedef struct {
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states
IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node

2
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
View File

@ -78,7 +78,7 @@ typedef struct {
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states
IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node