soc/intel/quark: Add I2C support
Add the I2C driver. TEST=Build and run on Galileo Gen2 Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14828 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
Leroy P Leahy
parent
0e962eeb93
commit
ac690b1e9b
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@ -25,6 +25,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += chip.c
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ramstage-y += gpio_i2c.c
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ramstage-y += memmap.c
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ramstage-y += memmap.c
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ramstage-y += northcluster.c
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ramstage-y += northcluster.c
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ramstage-y += pmc.c
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ramstage-y += pmc.c
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@ -0,0 +1,195 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/i2c.h>
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#include <soc/ramstage.h>
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#include <soc/reg_access.h>
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static void i2c_disable(I2C_REGS *regs)
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{
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uint32_t status;
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uint32_t timeout;
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/* Disable I2C controller */
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regs->ic_enable = 0;
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/* Wait for the enable bit to clear */
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timeout = 1 * 1000 * 1000;
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status = regs->ic_enable_status;
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while (status & IC_ENABLE_CONTROLLER) {
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udelay(1);
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if (--timeout == 0)
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die("ERROR - I2C failed to disable!\n");
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status = regs->ic_enable_status;
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}
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/* Clear any pending interrupts */
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status = regs->ic_clr_intr;
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}
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int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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{
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uint8_t *buffer;
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int bytes_transferred;
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uint8_t chip;
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uint32_t cmd;
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int length;
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int read_length;
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I2C_REGS *regs;
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uint32_t status;
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uint32_t timeout;
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regs = get_i2c_address();
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/* Disable the I2C controller to get access to the registers */
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i2c_disable(regs);
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/* Set the slave address */
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ASSERT (count > 0);
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ASSERT (segments != NULL);
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ASSERT (segments->read == 0);
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/* Clear the start and stop detection */
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status = regs->ic_clr_start_det;
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status = regs->ic_clr_stop_det;
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/* Set addressing mode to 7-bit and fast mode */
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cmd = regs->ic_con;
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cmd &= ~(IC_CON_10B | IC_CON_SPEED);
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cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz
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| IC_CON_MASTER_MODE;
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regs->ic_con = cmd;
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/* Set the target chip address */
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chip = segments->chip;
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regs->ic_tar = chip;
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/* Enable the I2C controller */
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regs->ic_enable = IC_ENABLE_CONTROLLER;
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/* Clear the interrupts */
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status = regs->ic_clr_rx_under;
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status = regs->ic_clr_rx_over;
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status = regs->ic_clr_tx_over;
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status = regs->ic_clr_tx_abrt;
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/* Process each of the segments */
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bytes_transferred = 0;
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read_length = 0;
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buffer = NULL;
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while (count-- > 0) {
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buffer = segments->buf;
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length = segments->len;
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ASSERT (buffer != NULL);
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ASSERT (length >= 1);
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ASSERT (segments->chip = chip);
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if (segments->read) {
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/* Place read commands into the FIFO */
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read_length = length;
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while (length > 0) {
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/* Send stop bit after last byte */
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cmd = IC_DATA_CMD_READ;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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/* Place read command in transmit FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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}
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} else {
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/* Write the data into the FIFO */
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while (length > 0) {
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/* End of the transaction? */
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cmd = IC_DATA_CMD_WRITE | *buffer++;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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/* Place a data byte into the FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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bytes_transferred++;
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}
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}
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segments++;
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}
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/* Wait for the end of the transaction */
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timeout = 1 * 1000 * 1000;
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do {
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status = regs->ic_raw_intr_stat;
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if (status & IC_INTR_STOP_DET)
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break;
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if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
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| IC_INTR_TX_ABRT | IC_INTR_TX_OVER))
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|| (timeout == 0)) {
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if (timeout == 0)
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printk (BIOS_ERR,
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"ERROR - I2C stop bit not received!\n");
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if (status & IC_INTR_RX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C receive overrun!\n");
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if (status & IC_INTR_RX_UNDER)
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printk (BIOS_ERR,
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"ERROR - I2C receive underrun!\n");
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if (status & IC_INTR_TX_ABRT)
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printk (BIOS_ERR,
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"ERROR - I2C transmit abort!\n");
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if (status & IC_INTR_TX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C transmit overrun!\n");
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i2c_disable(regs);
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return -1;
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}
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timeout--;
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udelay(1);
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} while(1);
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/* Finish reading the data bytes */
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while (read_length > 0) {
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status = regs->ic_status;
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*buffer++ = (UINT8)regs->ic_data_cmd;
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read_length--;
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bytes_transferred++;
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status = regs->ic_status;
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}
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return bytes_transferred;
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}
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__attribute__((weak)) void mainboard_gpio_i2c_init(device_t dev)
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{
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/* Initialize any of the GPIOs or I2C devices */
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printk(BIOS_SPEW, "WEAK; mainboard_gpio_i2c_init\n");
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}
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static struct device_operations device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = mainboard_gpio_i2c_init,
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};
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static const struct pci_driver gfx_driver __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = I2CGPIO_DEVID,
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};
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@ -0,0 +1,131 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _QUARK_I2C_H_
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#define _QUARK_I2C_H_
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typedef volatile struct _I2C_REGS {
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volatile uint32_t ic_con; /* 00: Control Register */
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volatile uint32_t ic_tar; /* 04: Master Target Address */
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uint32_t reserved_08[2];
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volatile uint32_t ic_data_cmd; /* 10: Data Buffer & Command */
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uint32_t ic_ss_scl_hcnt; /* 14: Standard Speed Clock SCL High Count */
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uint32_t ic_ss_scl_lcnt; /* 18: Standard Speed Clock SCL Low Count */
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uint32_t ic_fs_scl_hcnt; /* 1c: Fast Speed Clock SCL High Count */
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uint32_t ic_fs_scl_lcnt; /* 20: Fast Speed Clock SCL Low Count */
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uint32_t reserved_24[2];
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volatile uint32_t ic_intr_stat; /* 2c: Interrupt Status */
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uint32_t ic_intr_mask; /* 30: Interrupt Mask */
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uint32_t ic_raw_intr_stat; /* 34: Raw Interrupt Status */
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uint32_t ic_rx_tl; /* 38: Receive FIFO Threshold Level */
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uint32_t ic_tx_tl; /* 3c: Transmit FIFO Threshold Level */
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uint32_t ic_clr_intr; /* 40: Clear Combined/Individual Interrupt */
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uint32_t ic_clr_rx_under; /* 44: Clear RX_UNDER Interrupt */
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uint32_t ic_clr_rx_over; /* 48: Clear RX_OVER Interrupt */
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uint32_t ic_clr_tx_over; /* 4c: Clear TX_OVER Interrupt */
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uint32_t ic_clr_rd_req; /* 50: Clear RD_REQ Interrupt */
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uint32_t ic_clr_tx_abrt; /* 54: Clear TX_ABRT Interrupt */
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uint32_t reserved_58;
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uint32_t ic_clr_activity; /* 5c: Clear ACTIVITY Interrupt */
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uint32_t ic_clr_stop_det; /* 60: Clear STOP_DET Interrupt */
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uint32_t ic_clr_start_det; /* 64: Clear START_DET Interrupt */
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uint32_t reserved_68;
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volatile uint32_t ic_enable; /* 6c: Enable */
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volatile uint32_t ic_status; /* 70: Status */
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uint32_t ic_txflr; /* 74: Transmit FIFO Level */
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uint32_t ic_rxflr; /* 78: Receive FIFO Level */
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uint32_t ic_sda_hold; /* 7c: SDA Hold */
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volatile uint32_t ic_tx_abrt_source; /* 80: Transmit Abort Source */
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uint32_t reserved_84[6];
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volatile uint32_t ic_enable_status; /* 9c: Enable Status */
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uint32_t ic_fs_spklen; /* a0: SS and FS Spike Suppression Limit */
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} I2C_REGS;
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#define IC_CON offsetof(I2C_REGS, ic_con)
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#define IC_TAR offsetof(I2C_REGS, ic_tar)
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#define IC_DATA_CMD offsetof(I2C_REGS, ic_data_cmd)
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#define IC_SS_SCL_HCNT offsetof(I2C_REGS, ic_ss_scl_hcnt)
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#define IC_SS_SCL_LCNT offsetof(I2C_REGS, ic_ss_scl_lcnt)
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#define IC_FS_SCL_HCNT offsetof(I2C_REGS, ic_fs_scl_hcnt)
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#define IC_FS_SCL_LCNT offsetof(I2C_REGS, ic_fs_scl_lcnt)
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#define IC_INTR_STAT offsetof(I2C_REGS, ic_intr_stat)
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#define IC_INTR_MASK offsetof(I2C_REGS, ic_intr_mask)
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#define IC_RAW_INTR_STAT offsetof(I2C_REGS, ic_raw_intr_stat)
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#define IC_RX_TL offsetof(I2C_REGS, ic_rx_tl)
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#define IC_TX_TL offsetof(I2C_REGS, ic_tx_tl)
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#define IC_CLR_INTR offsetof(I2C_REGS, ic_clr_intr)
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#define IC_CLR_RX_UNDER offsetof(I2C_REGS, ic_clr_rx_under)
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#define IC_CLR_RX_OVER offsetof(I2C_REGS, ic_clr_rx_over)
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#define IC_CLR_TX_OVER offsetof(I2C_REGS, ic_clr_tx_over)
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#define IC_CLR_RD_REQ offsetof(I2C_REGS, ic_clr_rd_req)
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#define IC_CLR_TX_ABRT offsetof(I2C_REGS, ic_clr_tx_abrt)
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#define IC_CLR_ACTIVITY offsetof(I2C_REGS, ic_clr_activity)
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#define IC_CLR_STOP_DET offsetof(I2C_REGS, ic_clr_stop_det)
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#define IC_CLR_START_DET offsetof(I2C_REGS, ic_clr_start_det)
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#define IC_ENABLE offsetof(I2C_REGS, ic_enable)
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#define IC_STATUS offsetof(I2C_REGS, ic_status)
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#define IC_TXFLR offsetof(I2C_REGS, ic_txflr)
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#define IC_RXFLR offsetof(I2C_REGS, ic_rxflr)
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#define IC_SDA_HOLD offsetof(I2C_REGS, ic_sda_hold)
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#define IC_TX_ABRT_SOURCE offsetof(I2C_REGS, ic_tx_abrt_source)
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#define IC_ENABLE_STATUS offsetof(I2C_REGS, ic_enable_status)
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#define IC_FS_SPKLEN offsetof(I2C_REGS, ic_fs_spklen)
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/* 0x00: ic_con */
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#define IC_CON_RESTART_EN 0x00000020 /* Enable start/restart */
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#define IC_CON_10B 0x00000010 /* 10-bit addressing */
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#define IC_CON_7B 0 /* 7-bit addressing */
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#define IC_CON_SPEED 0x00000006 /* I2C bus speed */
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#define IC_CON_SPEED_400_KHz 0x00000004 /* Fast mode */
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#define IC_CON_SPEED_100_KHz 0x00000002 /* Standard mode */
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#define IC_CON_MASTER_MODE 0x00000001 /* Enable master mode */
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/* 0x10: ic_data_cmd */
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#define IC_DATA_CMD_RESTART 0x00000400 /* Send restart before byte */
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#define IC_DATA_CMD_STOP 0x00000200 /* Send stop after byte */
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#define IC_DATA_CMD_CMD 0x00000100 /* Type of transaction */
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#define IC_DATA_CMD_READ IC_DATA_CMD_CMD
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#define IC_DATA_CMD_WRITE 0
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#define IC_DATA_CMD_DATA 0x000000ff /* Data byte */
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/* 0x2c: ic_intr_stat
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* 0x30: ic_intr_mask
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* 0x34: ic_raw_intr_stat
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*/
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#define IC_INTR_START_DET 0x00000400 /* Start bit detected */
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#define IC_INTR_STOP_DET 0x00000200 /* Stop bit detected */
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#define IC_INTR_ACTIVITY 0x00000100 /* Activity detected */
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#define IC_INTR_TX_ABRT 0x00000040 /* Transmit abort */
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#define IC_INTR_RD_REQ 0x00000020 /* Read request */
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#define IC_INTR_TX_EMPTY 0x00000010 /* TX FIFO is empty */
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#define IC_INTR_TX_OVER 0x00000008 /* TX FIFO overflow */
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#define IC_INTR_RX_FULL 0x00000004 /* Receive FIFO is full */
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#define IC_INTR_RX_OVER 0x00000002 /* Receive FIFO overflow */
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#define IC_INTR_RX_UNDER 0x00000001 /* Receive FIFO underflow */
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/* 0x6c: ic_enable
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* 0x9c: ic_enable_status
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*/
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#define IC_ENABLE_CONTROLLER 0x00000001 /* Enable the I2C controller */
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/* 0x70: ic_status */
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#define IC_STATUS_MST_ACTIVITY 0x00000020 /* Master FSM activity */
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||||||
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#define IC_STATUS_RFF 0x00000010 /* Receive FIFO completely full */
|
||||||
|
#define IC_STATUS_RFNE 0x00000008 /* Receive FIFO not empty */
|
||||||
|
#define IC_STATUS_TFE 0x00000004 /* Transmit FIFO completely empty */
|
||||||
|
#define IC_STATUS_TFNF 0x00000002 /* Transmit FIFO not full */
|
||||||
|
#define IC_STATUS_ACTIVITY 0x00000001 /* Activity */
|
||||||
|
|
||||||
|
#endif /* _QUARK_I2C_H_ */
|
||||||
|
|
@ -22,4 +22,6 @@
|
||||||
#include <fsp/ramstage.h>
|
#include <fsp/ramstage.h>
|
||||||
#include <soc/QuarkNcSocId.h>
|
#include <soc/QuarkNcSocId.h>
|
||||||
|
|
||||||
|
void mainboard_gpio_i2c_init(device_t dev);
|
||||||
|
|
||||||
#endif /* _SOC_RAMSTAGE_H_ */
|
#endif /* _SOC_RAMSTAGE_H_ */
|
||||||
|
|
|
||||||
|
|
@ -150,6 +150,7 @@ enum {
|
||||||
#define REG_USB_XOR(reg_, value_) \
|
#define REG_USB_XOR(reg_, value_) \
|
||||||
REG_USB_RXW(reg_, 0xffffffff, value_)
|
REG_USB_RXW(reg_, 0xffffffff, value_)
|
||||||
|
|
||||||
|
void *get_i2c_address(void);
|
||||||
void mainboard_gpio_init(void);
|
void mainboard_gpio_init(void);
|
||||||
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
|
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
|
||||||
uint32_t mdr_read(void);
|
uint32_t mdr_read(void);
|
||||||
|
|
|
||||||
|
|
@ -20,6 +20,45 @@
|
||||||
#include <soc/pci_devs.h>
|
#include <soc/pci_devs.h>
|
||||||
#include <soc/reg_access.h>
|
#include <soc/reg_access.h>
|
||||||
|
|
||||||
|
static uint32_t *get_gpio_address(uint32_t reg_address)
|
||||||
|
{
|
||||||
|
uint32_t gpio_base_address;
|
||||||
|
|
||||||
|
/* Get the GPIO base address */
|
||||||
|
gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1);
|
||||||
|
gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
|
||||||
|
ASSERT (gpio_base_address != 0x00000000);
|
||||||
|
|
||||||
|
/* Return the GPIO register address */
|
||||||
|
return (uint32_t *)(gpio_base_address + reg_address);
|
||||||
|
}
|
||||||
|
|
||||||
|
void *get_i2c_address(void)
|
||||||
|
{
|
||||||
|
uint32_t gpio_base_address;
|
||||||
|
|
||||||
|
/* Get the GPIO base address */
|
||||||
|
gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0);
|
||||||
|
gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
|
||||||
|
ASSERT (gpio_base_address != 0x00000000);
|
||||||
|
|
||||||
|
/* Return the GPIO register address */
|
||||||
|
return (void *)gpio_base_address;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint16_t get_legacy_gpio_address(uint32_t reg_address)
|
||||||
|
{
|
||||||
|
uint32_t gpio_base_address;
|
||||||
|
|
||||||
|
/* Get the GPIO base address */
|
||||||
|
gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE);
|
||||||
|
ASSERT (gpio_base_address >= 0x80000000);
|
||||||
|
gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK;
|
||||||
|
|
||||||
|
/* Return the GPIO register address */
|
||||||
|
return (uint16_t)(gpio_base_address + reg_address);
|
||||||
|
}
|
||||||
|
|
||||||
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
|
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
|
||||||
{
|
{
|
||||||
pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
|
pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
|
||||||
|
|
@ -45,19 +84,6 @@ void mea_write(uint32_t reg_address)
|
||||||
& QNC_MEA_MASK);
|
& QNC_MEA_MASK);
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t *get_gpio_address(uint32_t reg_address)
|
|
||||||
{
|
|
||||||
uint32_t gpio_base_address;
|
|
||||||
|
|
||||||
/* Get the GPIO base address */
|
|
||||||
gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1);
|
|
||||||
gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
|
|
||||||
ASSERT (gpio_base_address != 0x00000000);
|
|
||||||
|
|
||||||
/* Return the GPIO register address */
|
|
||||||
return (uint32_t *)(gpio_base_address + reg_address);
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t reg_gpio_read(uint32_t reg_address)
|
static uint32_t reg_gpio_read(uint32_t reg_address)
|
||||||
{
|
{
|
||||||
/* Read the GPIO register */
|
/* Read the GPIO register */
|
||||||
|
|
@ -70,19 +96,6 @@ static void reg_gpio_write(uint32_t reg_address, uint32_t value)
|
||||||
*get_gpio_address(reg_address) = value;
|
*get_gpio_address(reg_address) = value;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint16_t get_legacy_gpio_address(uint32_t reg_address)
|
|
||||||
{
|
|
||||||
uint32_t gpio_base_address;
|
|
||||||
|
|
||||||
/* Get the GPIO base address */
|
|
||||||
gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE);
|
|
||||||
ASSERT (gpio_base_address >= 0x80000000);
|
|
||||||
gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK;
|
|
||||||
|
|
||||||
/* Return the GPIO register address */
|
|
||||||
return (uint16_t)(gpio_base_address + reg_address);
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t reg_legacy_gpio_read(uint32_t reg_address)
|
uint32_t reg_legacy_gpio_read(uint32_t reg_address)
|
||||||
{
|
{
|
||||||
/* Read the legacy GPIO register */
|
/* Read the legacy GPIO register */
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue