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libpayload: OHCI driver correct PCI BAR reading 

Correct registers base (PCI BAR) reading to be
more specification friendly. Registers base
only in [31-12] bits, all other proposed to be 0
but that not true for some motherboards. So
adding mask to use only valid bits.

Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1143
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Anton Kochkov 2012-06-27 07:16:03 +04:00 committed by Patrick Georgi
parent 8fef662505
commit ac6e3172ff
1 changed files with 3 additions and 1 deletions
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4
payloads/libpayload/drivers/usb/ohci.c
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@ -111,7 +111,9 @@ ohci_init (pcidev_t addr)
OHCI_INST (controller)->roothub = controller->devices[0];
controller->bus_address = addr;
controller->reg_base = pci_read_config32 (controller->bus_address, 0x10); // OHCI mandates MMIO, so bit 0 is clear
/* regarding OHCI spec, Appendix A, BAR_OCHI register description, Table A-4
* BASE ADDRESS only [31-12] bits. All other usually 0, but not all */
controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear
OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base);
printf("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf);