GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration 

coreboot already unconditionally enables CLKRUN_EN in SoC common code.

Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.

Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Benjamin Doron 2020-12-12 22:42:41 +00:00 committed by Nico Huber
parent a04400d1aa
commit ac857ca3b1
4 changed files with 0 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/51nb/x210/devicetree.cb
View File

@ -56,8 +56,6 @@ chip soc/intel/skylake
register "serirq_mode" = "SERIRQ_CONTINUOUS" register "serirq_mode" = "SERIRQ_CONTINUOUS"
register "PmConfigPciClockRun" = "1"
# Enable Root Ports 3, 4 and 9 # Enable Root Ports 3, 4 and 9
register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpEnable[2]" = "1" # Ethernet controller
register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqSupport[2]" = "1"

1
src/mainboard/kontron/bsl6/devicetree.cb
View File

@ -10,7 +10,6 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
register "PmConfigPciClockRun" = "1"
register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
# VR Settings Configuration for 2 Domains # VR Settings Configuration for 2 Domains

1
src/soc/intel/skylake/chip.c
View File

@ -338,7 +338,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;
params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert;
params->PchPmLpcClockRun = config->PmConfigPciClockRun;
params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
params->PchPmPwrBtnOverridePeriod = params->PchPmPwrBtnOverridePeriod =
config->PmConfigPwrBtnOverridePeriod; config->PmConfigPwrBtnOverridePeriod;

5
src/soc/intel/skylake/chip.h
View File

@ -376,11 +376,6 @@ struct soc_intel_skylake_config {
SLP_A_MIN_ASSERT_2S = 3, SLP_A_MIN_ASSERT_2S = 3,
} PmConfigSlpAMinAssert; } PmConfigSlpAMinAssert;
/*
* This member describes whether or not the PCI ClockRun feature of PCH
* should be enabled. Values 0: Disabled, 1: Enabled
*/
u8 PmConfigPciClockRun;
/* /*
* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
* 1: Enabled * 1: Enabled