soc/intel/cannonlake: Add PMC pci drivers
Add PMC pci driver on top of PMC common code, also include pmc init code reference from skylake. Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -31,7 +31,9 @@ ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += gpio.c
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ramstage-y += memmap.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += spi.c
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@ -63,8 +63,10 @@ struct soc_intel_cannonlake_config {
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int dptf_enable;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable;
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int deep_s5_enable;
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int deep_s3_enable_ac;
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int deep_s3_enable_dc;
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int deep_s5_enable_ac;
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int deep_s5_enable_dc;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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@ -96,3 +96,20 @@ const struct pad_community *soc_gpio_get_community(size_t *num_communities)
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*num_communities = ARRAY_SIZE(cnl_communities);
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return cnl_communities;
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}
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const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
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{
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static const struct pmc_to_gpio_route routes[] = {
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{ GPP_A, GPP_A },
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{ GPP_B, GPP_B },
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{ GPP_C, GPP_C },
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{ GPP_D, GPP_D },
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{ GPP_E, GPP_E },
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{ GPP_F, GPP_F },
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{ GPP_G, GPP_G },
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{ GPP_H, GPP_H },
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{ GPD, GPD },
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};
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*num = ARRAY_SIZE(routes);
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return routes;
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}
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@ -105,6 +105,7 @@
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#define DSX_EN_WAKE_PIN (1 << 2)
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#define DSX_EN_AC_PRESENT_PIN (1 << 1)
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#define DSX_EN_LAN_WAKE_PIN (1 << 0)
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#define DSX_CFG_MASK (0x1f << 0)
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#define PMSYNC_TPR_CFG 0x18C4
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#define PCH2CPU_TPR_CFG_LOCK (1 << 31)
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@ -0,0 +1,180 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <pc80/mc146818rtc.h>
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#include <string.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <cpu/x86/smm.h>
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#include <soc/pcr_ids.h>
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#include <soc/ramstage.h>
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#include <vboot/vbnv.h>
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#include <vboot/vbnv_layout.h>
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static void pch_pmc_add_mmio_resources(device_t dev)
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{
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struct resource *res;
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/* Memory-mmapped I/O registers. */
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res = new_resource(dev, PWRMBASE);
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res->base = PCH_PWRM_BASE_ADDRESS;
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res->size = PCH_PWRM_BASE_SIZE;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED | IORESOURCE_RESERVE;
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}
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static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
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{
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struct resource *res;
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res = new_resource(dev, index);
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res->base = base;
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res->size = size;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void pch_pmc_add_io_resources(device_t dev)
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{
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/* PMBASE */
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pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
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}
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static void pch_pmc_read_resources(device_t dev)
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{
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add non-standard MMIO resources. */
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pch_pmc_add_mmio_resources(dev);
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/* Add IO resources. */
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pch_pmc_add_io_resources(dev);
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}
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static void pch_set_acpi_mode(void)
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{
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if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
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printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
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outb(APM_CNT_ACPI_DISABLE, APM_CNT);
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printk(BIOS_DEBUG, "done.\n");
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}
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}
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int soc_get_rtc_failed(void)
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{
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uint8_t reg8;
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int rtc_failed;
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uint8_t *pmcbase = pmc_mmio_regs();
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reg8 = read8(pmcbase + GEN_PMCON_B);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~RTC_BATTERY_DEAD;
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write8(pmcbase + GEN_PMCON_B, reg8);
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printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
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}
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return rtc_failed;
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}
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static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
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{
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uint32_t reg;
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uint8_t *pmcbase = pmc_mmio_regs();
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printk(BIOS_DEBUG, "%sabling Deep S%c\n",
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enable ? "En" : "Dis", sx + '0');
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reg = read32(pmcbase + offset);
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if (enable)
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reg |= mask;
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else
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reg &= ~mask;
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write32(pmcbase + offset, reg);
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}
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static void config_deep_s5(int on_ac, int on_dc)
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{
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/* Treat S4 the same as S5. */
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config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
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config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
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config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
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config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
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}
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static void config_deep_s3(int on_ac, int on_dc)
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{
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config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
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config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
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}
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static void config_deep_sx(uint32_t deepsx_config)
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{
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uint32_t reg;
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uint8_t *pmcbase = pmc_mmio_regs();
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reg = read32(pmcbase + DSX_CFG);
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reg &= ~DSX_CFG_MASK;
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reg |= deepsx_config;
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write32(pmcbase + DSX_CFG, reg);
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}
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static void pmc_init(struct device *dev)
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{
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config_t *config = dev->chip_info;
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rtc_init();
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/* Initialize power management */
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pmc_gpe_init();
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pch_set_acpi_mode();
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config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
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config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
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config_deep_sx(config->deep_sx_config);
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}
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static struct device_operations device_ops = {
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.read_resources = &pch_pmc_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &pmc_init,
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.scan_bus = &scan_lpc_bus,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_CNL_PMC,
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0
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};
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static const struct pci_driver pch_lpc __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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