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mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics 

1. GPP_E5 =>  Remove unused GPIOs
2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO

Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2021-01-27 12:50:06 +05:30 committed by Patrick Georgi
parent 316466b765
commit ac8c357ddc
1 changed files with 3 additions and 4 deletions
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7
src/mainboard/intel/adlrvp/gpio.c
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@ -226,10 +226,9 @@ static const struct pad_config gpio_table[] = {
/* SMB_DATA */
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* SATADevSlpPin to GPIO pin mapping */
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
/* SATA DIRECT DEVSLP*/
PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5),
/* SATA DEVSLP */
PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
/* SATA LED pin */
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),