libpayload/arch/x86: Add support for initializing the APIC
This is just the bare minimum required to initialize the APIC. I only support xAPIC and chose not to support x2APIC. We can add that functionality later when it's required. I also made the exception dispatcher call apic_eoi so that the callbacks won't forget to call it. BUG=b:109749762 TEST=Booted grunt and verified that depthcharge continued to function and that linux booted correctly. Also verified GDB still works. Change-Id: I420a4eadae84df088525e727b481089ef615183f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Raul E Rangel
Martin Roth
parent
3d398ad37a
commit
ac8ebd0e73
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@ -34,4 +34,7 @@ config ARCH_SPECIFIC_OPTIONS # dummy
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select LITTLE_ENDIAN
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select IO_ADDRESS_SPACE
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config ENABLE_APIC
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bool "Enables the Local APIC"
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endif
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@ -45,3 +45,5 @@ libcbfs-$(CONFIG_LP_CBFS) += rom_media.c
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# Multiboot support is configurable
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libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c
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libc-$(CONFIG_LP_ENABLE_APIC) += apic.c
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@ -0,0 +1,189 @@
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/*
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* This file is part of the libpayload project.
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*
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* Copyright 2018 Google LLC.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <libpayload.h>
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#include <arch/apic.h>
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#include <arch/cpuid.h>
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#include <arch/msr.h>
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#include <exception.h>
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#define APIC_BASE_MSR 0x0000001B
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#define APIC_BASE_MASK (0xFFFFFFFULL << 12)
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#define CPUID_XAPIC_ENABLED_BIT (1 << 9)
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#define CPUID_XAPIC2_ENABLED_BIT (1 << 21)
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#define XAPIC_ENABLED_BIT (1 << 11)
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#define X2APIC_ENABLED_BIT (1 << 10)
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#define APIC_MASKED_BIT (1 << 16)
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#define APIC_SW_ENABLED_BIT (1 << 8)
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#define APIC_ID 0x020
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#define APIC_ID_SHIFT 24
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#define APIC_ID_MASK (0xFFUL << APIC_ID_SHIFT)
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#define APIC_VERSION 0x030
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#define APIC_MAX_LVT_SHIFT 16
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#define APIC_MAX_LVT_MASK (0xFFUL << APIC_MAX_LVT_SHIFT)
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#define APIC_TASK_PRIORITY 0x080
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#define APIC_TASK_PRIORITY_MASK 0xFFUL
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#define APIC_EOI 0x0B0
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#define APIC_SPURIOUS 0x0F0
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#define APIC_LVT_TIMER 0x320
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#define APIC_TIMER_INIT_COUNT 0x380
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#define APIC_TIMER_CUR_COUNT 0x390
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#define APIC_TIMER_DIV_CFG 0x3E0
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#define APIC_LVT_SIZE 0x010
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static uint32_t apic_bar;
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static int _apic_initialized;
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enum APIC_CAPABILITY {
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DISABLED = 0,
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XACPI = 1 << 0,
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X2ACPI = 1 << 1
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};
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int apic_initialized(void)
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{
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return _apic_initialized;
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}
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static inline uint32_t apic_read32(uint32_t offset)
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{
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return read32((void *)(apic_bar + offset));
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}
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static inline void apic_write32(uint32_t offset, uint32_t value)
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{
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write32((void *)(apic_bar + offset), value);
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}
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uint8_t apic_id(void)
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{
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die_if(!apic_bar, "APIC is not initialized");
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uint8_t id =
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(apic_read32(APIC_ID) & APIC_ID_MASK) >> APIC_ID_SHIFT;
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return id;
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}
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void apic_eoi(void)
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{
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die_if(!apic_bar, "APIC is not initialized");
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apic_write32(APIC_EOI, 0);
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}
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static enum APIC_CAPABILITY apic_capabilities(void)
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{
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uint32_t eax, ebx, ecx, edx;
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cpuid(1, eax, ebx, ecx, edx);
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enum APIC_CAPABILITY capabilities = DISABLED;
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if (edx & CPUID_XAPIC_ENABLED_BIT)
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capabilities |= XACPI;
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if (ecx & CPUID_XAPIC2_ENABLED_BIT)
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capabilities |= X2ACPI;
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return capabilities;
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}
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static uint8_t apic_max_lvt_entries(void)
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{
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die_if(!apic_bar, "APIC is not initialized");
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uint32_t reg = apic_read32(APIC_VERSION);
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reg &= APIC_MAX_LVT_MASK;
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reg >>= APIC_MAX_LVT_SHIFT;
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return (uint8_t)reg;
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}
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static void apic_reset_all_lvts(void)
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{
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uint8_t max = apic_max_lvt_entries();
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for (int i = 0; i <= max; ++i) {
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uint32_t offset = APIC_LVT_TIMER + APIC_LVT_SIZE * i;
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apic_write32(offset, APIC_MASKED_BIT);
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}
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}
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static void apic_set_task_priority(uint8_t priority)
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{
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die_if(!apic_bar, "APIC is not initialized");
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uint32_t tpr = apic_read32(APIC_TASK_PRIORITY);
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tpr &= ~APIC_TASK_PRIORITY_MASK;
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tpr |= priority;
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apic_write32(APIC_TASK_PRIORITY, priority);
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}
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static void apic_sw_enable(void)
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{
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uint32_t reg = apic_read32(APIC_SPURIOUS);
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if (reg & APIC_SW_ENABLED_BIT)
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return;
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reg |= APIC_SW_ENABLED_BIT;
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apic_write32(APIC_SPURIOUS, reg);
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}
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void apic_init(void)
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{
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uint64_t apic_bar_reg;
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printf("APIC Init Started\n");
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die_if(apic_initialized(), "APIC already initialized");
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die_if(!(apic_capabilities() & XACPI), "APIC is not supported");
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apic_bar_reg = _rdmsr(APIC_BASE_MSR);
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die_if(!(apic_bar_reg & XAPIC_ENABLED_BIT), "APIC is not enabled");
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die_if(apic_bar_reg & X2APIC_ENABLED_BIT,
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"APIC is configured in x2APIC mode which is not supported");
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apic_bar = (uint32_t)(apic_bar_reg & APIC_BASE_MASK);
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apic_reset_all_lvts();
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apic_set_task_priority(0);
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apic_sw_enable();
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_apic_initialized = 1;
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printf("APIC Configured\n");
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}
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@ -31,8 +31,16 @@
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#include <exception.h>
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#include <libpayload.h>
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#include <stdint.h>
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#include <arch/apic.h>
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#define IF_FLAG (1 << 9)
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/*
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* Local and I/O APICs support 240 vectors (in the range of 16 to 255) as valid
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* interrupts. The Intel 64 and IA-32 architectures reserve vectors 16
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* through 31 for predefined interrupts, exceptions, and Intel-reserved
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* encodings.
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*/
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#define FIRST_USER_DEFINED_VECTOR 32
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u32 exception_stack[0x400] __attribute__((aligned(8)));
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@ -171,6 +179,9 @@ void exception_dispatch(void)
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if (handlers[vec]) {
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handlers[vec](vec);
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if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)
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&& vec >= FIRST_USER_DEFINED_VECTOR)
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apic_eoi();
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return;
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}
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@ -29,6 +29,7 @@
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#include <exception.h>
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#include <libpayload.h>
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#include <arch/apic.h>
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unsigned long loader_eax; /**< The value of EAX passed from the loader */
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unsigned long loader_ebx; /**< The value of EBX passed from the loader */
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@ -57,6 +58,12 @@ int start_main(void)
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exception_init();
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if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) {
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apic_init();
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enable_interrupts();
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}
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/*
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* Any other system init that has to happen before the
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* user gets control goes here.
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@ -0,0 +1,43 @@
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/*
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* This file is part of the libpayload project.
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*
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* Copyright 2018 Google LLC.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_INCLUDES_ARCH_APIC_H__
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#define __ARCH_X86_INCLUDES_ARCH_APIC_H__
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/** Returns 1 if apic_init has been called */
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int apic_initialized(void);
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void apic_init(void);
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uint8_t apic_id(void);
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/** Signal the end of the interrupt handler. */
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void apic_eoi(void);
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#endif /* __ARCH_X86_INCLUDES_ARCH_APIC_H__ */
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