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amd/thatcher: Switch away from AGESA_LEGACY 

Change-Id: I7194eb910cccc454c5f20c23629ff2a45b1a9079
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-03-04 07:50:54 +02:00
parent 46379c74ad
commit acc8ac649d
5 changed files with 51 additions and 120 deletions
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47
src/mainboard/amd/thatcher/BiosCallOuts.c
View File

@ -16,6 +16,7 @@
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h" #include "amdlib.h"
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "Ids.h" #include "Ids.h"
#include "heapManager.h" #include "heapManager.h"
#include "FchPlatform.h" #include "FchPlatform.h"
@ -25,8 +26,6 @@
#endif #endif
#include <stdlib.h> #include <stdlib.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] = const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{ {
{AGESA_DO_RESET, agesa_Reset }, {AGESA_DO_RESET, agesa_Reset },
@ -36,7 +35,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
}; };
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
@ -177,37 +175,16 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
#endif /* CONFIG_HUDSON_IMC_FWM */ #endif /* CONFIG_HUDSON_IMC_FWM */
} }
/**
* Fch Oem setting callback void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
*
* Configure platform specific Hudson device,
* such Azalia, SATA, IMC etc.
*/
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{ {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
}
if (FchParams->StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); {
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ /* Azalia Controller OEM Codec Table Pointer */
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
} else if (FchParams->StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; oem_fan_control(FchParams_env);
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
/* Azalia Controller OEM Codec Table Pointer */
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
/* Azalia Controller Front Panel OEM Table Pointer */
/* Fan Control */
oem_fan_control(FchParams_env);
/* XHCI configuration */
FchParams_env->Usb.Xhci0Enable = FALSE;
FchParams_env->Usb.Xhci1Enable = FALSE;
}
printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
} }

1
src/mainboard/amd/thatcher/Kconfig
View File

@ -17,7 +17,6 @@ if BOARD_AMD_THATCHER
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY15_TN select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON select SOUTHBRIDGE_AMD_AGESA_HUDSON

35
src/mainboard/amd/thatcher/OemCustomize.c
View File

@ -20,7 +20,7 @@
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "Filecode.h" #include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
@ -147,6 +147,13 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
&DdiList[0] &DdiList[0]
}; };
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
FchReset->Xhci0Enable = FALSE;
FchReset->Xhci1Enable = FALSE;
}
/*---------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------*/
/** /**
* OemCustomizeInitEarly * OemCustomizeInitEarly
@ -163,7 +170,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
**/ **/
/*---------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------*/
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
VOID *TrinityPcieComplexListPtr; VOID *TrinityPcieComplexListPtr;
@ -215,14 +222,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
return AGESA_SUCCESS;
}
static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
{
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
return AGESA_SUCCESS;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------
@ -236,7 +235,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings. * use its default conservative settings.
*/ */
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
@ -247,7 +246,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
PSO_END PSO_END
}; };
const struct OEM_HOOK OemCustomize = { void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
.InitEarly = OemInitEarly, {
.InitMid = OemInitMid, InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
}; }
void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
{
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
}

6
src/mainboard/amd/thatcher/mainboard.c
View File

@ -22,7 +22,8 @@
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/agesa/s3_resume.h>
#include <northbridge/amd/agesa/state_machine.h>
/************************************************* /*************************************************
* enable the dedicated function in thatcher board. * enable the dedicated function in thatcher board.
@ -45,9 +46,6 @@ static void mainboard_enable(device_t dev)
msr = rdmsr(0xC0011023); msr = rdmsr(0xC0011023);
msr.lo &= ~(1 << 23); msr.lo &= ~(1 << 23);
wrmsr(0xC0011023, msr); wrmsr(0xC0011023, msr);
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {

82
src/mainboard/amd/thatcher/romstage.c
View File

@ -22,89 +22,41 @@
#include <arch/stages.h> #include <arch/stages.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h> #include <console/console.h>
#include <commonlib/loglevel.h> #include <commonlib/loglevel.h>
#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/hudson.h>
#include <superio/smsc/lpc47n217/lpc47n217.h> #include <superio/smsc/lpc47n217/lpc47n217.h>
#include <cpu/amd/agesa/s3_resume.h>
#include "cbmem.h"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
void board_BeforeAgesa(struct sysinfo *cb)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val;
u8 byte; u8 byte;
pci_devfn_t dev; pci_devfn_t dev;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
/* Set LPC decode enables. */ /* Set LPC decode enables. */
dev = PCI_DEV(0, 0x14, 3); dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80(); hudson_lpc_port80();
byte = pci_read_config8(dev, 0x48); byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */ byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte); pci_write_config8(dev, 0x48, byte);
if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
post_code(0x30); /* For serial port. */
pci_write_config32(dev, 0x44, 0xff03ffd5);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
post_code(0x31); post_code(0x31);
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
outb(0xea, 0xcd6);
outb(0x1, 0xcd7);
*(u8 *)0xfed80101 = 0x98;
console_init();
}
/* Halt if there was a built in self test failure */ outb(0x24, 0xcd6);
post_code(0x34); outb(0x1, 0xcd7);
report_bist_failure(bist); outb(0xea, 0xcd6);
outb(0x1, 0xcd7);
/* Load MPB */ *(u8 *)0xfed80101 = 0x98;
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x41);
agesawrapper_amdinitenv();
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
amd_initcpuio();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
} }