amd/thatcher: Switch away from AGESA_LEGACY
Change-Id: I7194eb910cccc454c5f20c23629ff2a45b1a9079 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
parent
46379c74ad
commit
acc8ac649d
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@ -16,6 +16,7 @@
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include "Ids.h"
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#include "heapManager.h"
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#include "FchPlatform.h"
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@ -25,8 +26,6 @@
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#endif
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#include <stdlib.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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@ -36,7 +35,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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@ -177,37 +175,16 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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#endif /* CONFIG_HUDSON_IMC_FWM */
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}
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData;
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if (FchParams->StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
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} else if (FchParams->StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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}
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void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
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{
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
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/* Azalia Controller Front Panel OEM Table Pointer */
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/* Fan Control */
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oem_fan_control(FchParams_env);
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/* XHCI configuration */
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FchParams_env->Usb.Xhci0Enable = FALSE;
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FchParams_env->Usb.Xhci1Enable = FALSE;
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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@ -17,7 +17,6 @@ if BOARD_AMD_THATCHER
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select AGESA_LEGACY
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select CPU_AMD_AGESA_FAMILY15_TN
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select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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select SOUTHBRIDGE_AMD_AGESA_HUDSON
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@ -20,7 +20,7 @@
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#include <PlatformMemoryConfiguration.h>
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#include "Filecode.h"
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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@ -147,6 +147,13 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
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&DdiList[0]
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};
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void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
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FchReset->Xhci0Enable = FALSE;
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FchReset->Xhci1Enable = FALSE;
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}
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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@ -163,7 +170,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
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**/
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/*---------------------------------------------------------------------------------------*/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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AGESA_STATUS Status;
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VOID *TrinityPcieComplexListPtr;
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@ -215,14 +222,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
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InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
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return AGESA_SUCCESS;
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}
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static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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return AGESA_SUCCESS;
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}
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/*----------------------------------------------------------------------------------------
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@ -236,7 +235,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
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MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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@ -247,7 +246,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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PSO_END
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};
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const struct OEM_HOOK OemCustomize = {
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.InitEarly = OemInitEarly,
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.InitMid = OemInitMid,
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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}
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@ -22,7 +22,8 @@
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <arch/acpi.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include <northbridge/amd/agesa/state_machine.h>
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/*************************************************
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* enable the dedicated function in thatcher board.
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@ -45,9 +46,6 @@ static void mainboard_enable(device_t dev)
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msr = rdmsr(0xC0011023);
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msr.lo &= ~(1 << 23);
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wrmsr(0xC0011023, msr);
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if (acpi_is_wakeup_s3())
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agesawrapper_fchs3earlyrestore();
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}
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struct chip_operations mainboard_ops = {
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@ -22,89 +22,41 @@
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#include <arch/stages.h>
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#include <device/pnp_def.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/lapic.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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#include <superio/smsc/lpc47n217/lpc47n217.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include "cbmem.h"
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#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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u32 val;
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u8 byte;
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pci_devfn_t dev;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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/* Set LPC decode enables. */
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dev = PCI_DEV(0, 0x14, 3);
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pci_write_config32(dev, 0x44, 0xff03ffd5);
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hudson_lpc_port80();
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byte = pci_read_config8(dev, 0x48);
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byte |= 3; /* 2e, 2f */
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pci_write_config8(dev, 0x48, byte);
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if (!cpu_init_detectedx && boot_cpu()) {
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post_code(0x30);
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/* For serial port. */
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pci_write_config32(dev, 0x44, 0xff03ffd5);
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byte = pci_read_config8(dev, 0x48);
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byte |= 3; /* 2e, 2f */
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pci_write_config8(dev, 0x48, byte);
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post_code(0x31);
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lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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outb(0x24, 0xcd6);
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outb(0x1, 0xcd7);
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outb(0xea, 0xcd6);
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outb(0x1, 0xcd7);
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*(u8 *)0xfed80101 = 0x98;
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console_init();
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}
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/* Halt if there was a built in self test failure */
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post_code(0x34);
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report_bist_failure(bist);
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/* Load MPB */
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
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post_code(0x37);
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agesawrapper_amdinitreset();
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post_code(0x39);
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agesawrapper_amdinitearly();
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int s3resume = acpi_is_wakeup_s3();
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if (!s3resume) {
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post_code(0x40);
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agesawrapper_amdinitpost();
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post_code(0x41);
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agesawrapper_amdinitenv();
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disable_cache_as_ram();
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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post_code(0x60);
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agesawrapper_amdinitresume();
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amd_initcpuio();
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agesawrapper_amds3laterestore();
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post_code(0x61);
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prepare_for_resume();
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}
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post_code(0x50);
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copy_and_run();
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post_code(0x54); /* Should never see this post code. */
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}
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