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vendorcode/amd/agesa: Sync irrelevant differences 

After modifications:

  f12 and f14 are identical
  f10 is f14 with invd -> wbinvd modification added to HOOK_F10
  f15 is f10 with invd -> wbinvd modification added to HOOK_F15
  f15tn is f15 modified to use with TN / KV / KM

Change-Id: I4006fe09c134e5b51f3ee3772d6d150321d27b57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki 2017-07-13 22:48:22 +03:00
parent bfe6bcab74
commit acd13985b5
6 changed files with 54 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/vendorcode/amd/agesa/f10/gcccar.inc
View File

@ -42,7 +42,12 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
#ifdef __x86_64__
CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */
#else
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
#endif
APIC_BASE_ADDRESS = 0x0000001B
APIC_BSC = 8 /* Boot Strap Core */
@ -61,6 +66,20 @@ AMD_MTRR_FIX4k_E8000 = 0x026D
AMD_MTRR_FIX4k_F0000 = 0x026E
AMD_MTRR_FIX4k_F8000 = 0x026F
/* Reproduced from AGESA.h */
AMD_AP_MTRR_FIX64k_00000 = 0x00000250
AMD_AP_MTRR_FIX16k_80000 = 0x00000258
AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
CPU_LIST_TERMINAL = 0xFFFFFFFF
AMD_MTRR_DEFTYPE = 0x02FF
WB_DRAM_TYPE = 0x1E /* MemType - memory type */
MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */

20
src/vendorcode/amd/agesa/f12/gcccar.inc
View File

@ -42,7 +42,12 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
#ifdef __x86_64__
CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */
#else
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
#endif
APIC_BASE_ADDRESS = 0x0000001B
APIC_BSC = 8 /* Boot Strap Core */
@ -61,6 +66,20 @@ AMD_MTRR_FIX4k_E8000 = 0x026D
AMD_MTRR_FIX4k_F0000 = 0x026E
AMD_MTRR_FIX4k_F8000 = 0x026F
/* Reproduced from AGESA.h */
AMD_AP_MTRR_FIX64k_00000 = 0x00000250
AMD_AP_MTRR_FIX16k_80000 = 0x00000258
AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
CPU_LIST_TERMINAL = 0xFFFFFFFF
AMD_MTRR_DEFTYPE = 0x02FF
WB_DRAM_TYPE = 0x1E /* MemType - memory type */
MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
@ -1603,4 +1622,3 @@ ClearTheStack: # Stack base is in SS, stack pointer is
xor %eax, %eax
.endm

2
src/vendorcode/amd/agesa/f14/gcccar.inc
View File

@ -42,6 +42,7 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
#ifdef __x86_64__
CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */
#else
@ -1621,4 +1622,3 @@ ClearTheStack: # Stack base is in SS, stack pointer is
xor %eax, %eax
.endm

5
src/vendorcode/amd/agesa/f15/gcccar.inc
View File

@ -42,7 +42,12 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
#ifdef __x86_64__
CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */
#else
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
#endif
APIC_BASE_ADDRESS = 0x0000001B
APIC_BSC = 8 /* Boot Strap Core */

6
src/vendorcode/amd/agesa/f15tn/gcccar.inc
View File

@ -42,7 +42,12 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
#ifdef __x86_64__
CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */
#else
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
#endif
APIC_BASE_ADDRESS = 0x0000001B
APIC_BSC = 8 /* Boot Strap Core */
@ -1933,4 +1938,3 @@ ClearTheStack: # Stack base is in SS, stack pointer is
xor %eax, %eax
.endm

6
src/vendorcode/amd/agesa/f16kb/gcccar.inc
View File

@ -42,7 +42,12 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core
CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
#ifdef __x86_64__
CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */
#else
CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
#endif
APIC_BASE_ADDRESS = 0x0000001B
APIC_BSC = 8 /* Boot Strap Core */
@ -1298,4 +1303,3 @@ ClearTheStack: # Stack base is in SS, stack pointer is
xor %eax, %eax
.endm