mb/google/fizz: Provide baseboard and variant concepts
In order to be able to share code across different fizz variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/fizz - code variants/fizz/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot CQ-DEPEND=CL:1273514 Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -25,6 +25,10 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
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if BOARD_GOOGLE_BASEBOARD_FIZZ
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_EC_EFS
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@ -68,6 +72,10 @@ config TPM_TIS_ACPI_INTERRUPT
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int
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default 64 # GPE0_DW2_00 (GPP_E0)
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config VARIANT_DIR
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string
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default "fizz" if BOARD_GOOGLE_FIZZ
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config INCLUDE_NHLT_BLOBS
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bool "Include blobs for audio."
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select NHLT_RT5663
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@ -26,3 +26,9 @@ ramstage-y += mainboard.c
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ramstage-y += ramstage.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -16,7 +16,7 @@
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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static void early_config_gpio(void)
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{
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@ -18,7 +18,7 @@
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#include "ec.h"
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#include "gpio.h"
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#include <variant/ec.h>
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#include <variant/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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@ -61,7 +61,7 @@ DefinitionBlock(
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Scope (\_SB)
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{
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/* Dynamic Platform Thermal Framework */
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#include "acpi/dptf.asl"
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#include <variant/acpi/dptf.asl>
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}
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/* USB port entries */
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@ -16,7 +16,7 @@
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#include <arch/acpi.h>
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#include <ec/google/chromeec/ec.h>
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#include "ec.h"
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#include <variant/ec.h>
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void mainboard_ec_init(void)
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{
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@ -20,7 +20,7 @@
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <mainboard/google/fizz/gpio.h>
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#include <variant/gpio.h>
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#include <smbios.h>
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#include <soc/gpio.h>
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#include <soc/pci_devs.h>
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@ -18,12 +18,11 @@
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#include <delay.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <mainboard/google/fizz/gpio.h>
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#include <soc/gpio.h>
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#include <soc/ramstage.h>
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#include <timer.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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#define GPIO_HDMI_HPD GPP_E13
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#define GPIO_DP_HPD GPP_E14
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@ -17,7 +17,7 @@
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#include <ec/google/chromeec/smm.h>
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#include <soc/smm.h>
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#include "ec.h"
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#include <variant/ec.h>
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void mainboard_smi_espi_handler(void)
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{
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@ -13,13 +13,13 @@
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_EC_H__
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#define __MAINBOARD_EC_H__
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#ifndef __BASEBOARD_EC_H__
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#define __BASEBOARD_EC_H__
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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@ -281,6 +281,6 @@ static const struct pad_config early_gpio_table[] = {
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/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
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};
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#endif
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#endif /* __ACPI__ */
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#endif
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#endif /* BASEBOARD_GPIO_H */
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_EC_H__
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#define __MAINBOARD_EC_H__
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#include <baseboard/ec.h>
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#endif /* __MAINBOARD_EC_H__ */
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#include <baseboard/gpio.h>
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#endif /* __MAINBOARD_GPIO_H__ */
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