mb/google/fizz: Provide baseboard and variant concepts

In order to be able to share code across different fizz variants,
provide the concept of baseboard and variants. New directory layout:

variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/fizz - code
variants/fizz/include/variant - headers

New boards would then add themselves under their board name within
"variants" directory.

This is purely an organizational change.

BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
CQ-DEPEND=CL:1273514

Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
David Wu 2018-09-13 16:51:14 +08:00 committed by Patrick Georgi
parent 8f45bf2be7
commit aceaa71531
17 changed files with 88 additions and 17 deletions

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@ -25,6 +25,10 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
if BOARD_GOOGLE_BASEBOARD_FIZZ
config DEVICETREE
string
default "variants/baseboard/devicetree.cb"
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_EC_EFS
@ -68,6 +72,10 @@ config TPM_TIS_ACPI_INTERRUPT
int
default 64 # GPE0_DW2_00 (GPP_E0)
config VARIANT_DIR
string
default "fizz" if BOARD_GOOGLE_FIZZ
config INCLUDE_NHLT_BLOBS
bool "Include blobs for audio."
select NHLT_RT5663

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@ -26,3 +26,9 @@ ramstage-y += mainboard.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

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@ -16,7 +16,7 @@
#include <bootblock_common.h>
#include <soc/gpio.h>
#include "gpio.h"
#include <variant/gpio.h>
static void early_config_gpio(void)
{

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@ -18,7 +18,7 @@
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "gpio.h"
#include <variant/gpio.h>
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>

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@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
#include "ec.h"
#include "gpio.h"
#include <variant/ec.h>
#include <variant/gpio.h>
DefinitionBlock(
"dsdt.aml",
@ -61,7 +61,7 @@ DefinitionBlock(
Scope (\_SB)
{
/* Dynamic Platform Thermal Framework */
#include "acpi/dptf.asl"
#include <variant/acpi/dptf.asl>
}
/* USB port entries */

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@ -16,7 +16,7 @@
#include <arch/acpi.h>
#include <ec/google/chromeec/ec.h>
#include "ec.h"
#include <variant/ec.h>
void mainboard_ec_init(void)
{

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@ -20,7 +20,7 @@
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <mainboard/google/fizz/gpio.h>
#include <variant/gpio.h>
#include <smbios.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>

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@ -18,12 +18,11 @@
#include <delay.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <mainboard/google/fizz/gpio.h>
#include <soc/gpio.h>
#include <soc/ramstage.h>
#include <timer.h>
#include "gpio.h"
#include <variant/gpio.h>
#define GPIO_HDMI_HPD GPP_E13
#define GPIO_DP_HPD GPP_E14

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@ -17,7 +17,7 @@
#include <ec/google/chromeec/smm.h>
#include <soc/smm.h>
#include "ec.h"
#include <variant/ec.h>
void mainboard_smi_espi_handler(void)
{

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@ -13,13 +13,13 @@
* GNU General Public License for more details.
*/
#ifndef __MAINBOARD_EC_H__
#define __MAINBOARD_EC_H__
#ifndef __BASEBOARD_EC_H__
#define __BASEBOARD_EC_H__
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include "gpio.h"
#include <variant/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\

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@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
#ifndef __MAINBOARD_GPIO_H__
#define __MAINBOARD_GPIO_H__
#ifndef __BASEBOARD_GPIO_H__
#define __BASEBOARD_GPIO_H__
#include <soc/gpe.h>
#include <soc/gpio.h>
@ -281,6 +281,6 @@ static const struct pad_config early_gpio_table[] = {
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
};
#endif
#endif /* __ACPI__ */
#endif
#endif /* BASEBOARD_GPIO_H */

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@ -0,0 +1,16 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/acpi/dptf.asl>

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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MAINBOARD_EC_H__
#define __MAINBOARD_EC_H__
#include <baseboard/ec.h>
#endif /* __MAINBOARD_EC_H__ */

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@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef __MAINBOARD_GPIO_H__
#define __MAINBOARD_GPIO_H__
#include <baseboard/gpio.h>
#endif /* __MAINBOARD_GPIO_H__ */