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Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-36 

Creator:  Li-Ta Lo <ollie@lanl.gov>

emulator update

Correction to the reduce emulator from Paulo


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical) 2005-07-06 17:15:48 +00:00
parent 9c3f37cb5f
commit acfaeceffd
28 changed files with 480 additions and 899 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/i386/include/arch/acpi.h
View File

@ -89,6 +89,7 @@ typedef struct acpi_xsdt {
} __attribute__ ((packed)) acpi_xsdt_t;
/* HPET TIMERS */
typedef struct acpi_hpet {
struct acpi_table_header header;

6
src/console/vga_console.c
View File

@ -10,14 +10,16 @@
#include <pc80/vga.h>
#include <console/console.h>
//extern void beep(int ms);
/* The video buffer, should be replaced by symbol in ldscript.ld */
static char *vidmem;
int vga_line, vga_col;
#if CONFIG_CONSOLE_VGA == 1
extern int vga_inited; // it will be changed in pci_rom.c
#else
int vga_inited = 0;
#endif
static int vga_console_inited = 0;

2
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -95,7 +95,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
if (start_mtrr >= NUM_FIXED_RANGES) {
return;
}
printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
printk_debug("Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);

10
src/devices/device.c
View File

@ -363,6 +363,7 @@ void compute_allocate_resource(
}
#if CONFIG_CONSOLE_VGA == 1
device_t vga_pri = 0;
static void allocate_vga_resource(void)
@ -377,14 +378,13 @@ static void allocate_vga_resource(void)
vga = 0;
vga_onboard = 0;
for (dev = all_devices; dev; dev = dev->next) {
if ( !dev->enabled ) continue;
if (!dev->enabled) continue;
if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
if (!vga) {
if (dev->on_mainboard) {
vga_onboard = dev;
}
else {
} else {
vga = dev;
}
}
@ -397,7 +397,8 @@ static void allocate_vga_resource(void)
vga = vga_onboard;
}
if (vga) { // vga is first add on card or the only onboard vga
if (vga) {
// vga is first add on card or the only onboard vga
printk_debug("Allocating VGA resource %s\n", dev_path(vga));
vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
vga_pri = vga;
@ -411,7 +412,6 @@ static void allocate_vga_resource(void)
bus = (bus == bus->dev->bus)? 0 : bus->dev->bus;
}
}
#endif

4
src/devices/emulator/biosemu.c
View File

@ -161,6 +161,7 @@ void do_int(int num)
* BIOS. Most of this information was pulled from
* dosemu.
*/
#if 0
void setup_int_vect(void)
{
int i;
@ -222,6 +223,7 @@ int setup_system_bios(void *base_addr)
return 1;
}
#endif
void reset_int_vect(void)
{
@ -325,6 +327,8 @@ void run_bios(struct device * dev, unsigned long addr)
// X86EMU_trace_on();
printk_info("entering emulator\n");
X86EMU_exec();
#endif
}

4
src/devices/emulator/x86emu/debug.c
View File

@ -225,6 +225,7 @@ void X86EMU_dump_memory (u16 seg, u16 off, u32 amt)
void x86emu_single_step (void)
{
#if 0
char s[1024];
int ps[10];
int ntok;
@ -313,6 +314,7 @@ void x86emu_single_step (void)
break;
}
}
#endif
}
int X86EMU_trace_on(void)
@ -327,6 +329,7 @@ int X86EMU_trace_off(void)
static int parse_line (char *s, int *ps, int *n)
{
#if 0
int cmd;
*n = 0;
@ -352,6 +355,7 @@ static int parse_line (char *s, int *ps, int *n)
sscanf(s,"%x",&ps[*n]);
*n += 1;
}
#endif
}
#endif /* DEBUG */

2
src/devices/emulator/x86emu/decode.c
View File

@ -77,6 +77,8 @@ next instruction.
void x86emu_intr_raise(
u8 intrnum)
{
printk("%s, rasing execption %x\n", __func__, intrnum);
x86emu_dump_regs();
M.x86.intno = intrnum;
M.x86.intr |= INTR_SYNCH;
}

45
src/devices/emulator/x86emu/ops.c
View File

@ -70,7 +70,7 @@
*
****************************************************************************/
#include "x86emui.h"
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
@ -219,6 +219,7 @@ void x86emuOp_genop_byte_RM_R(u8 op1)
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = genop_byte_operation[op1](destval, *srcreg);
if (op1 != 7)
store_data_byte(destoffset, destval);
}
else
@ -262,6 +263,7 @@ void x86emuOp_genop_word_RM_R(u8 op1)
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = genop_long_operation[op1](destval, *srcreg);
if (op1 != 7)
store_data_long(destoffset, destval);
} else {
u16 destval;
@ -273,11 +275,12 @@ void x86emuOp_genop_word_RM_R(u8 op1)
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = genop_word_operation[op1](destval, *srcreg);
if (op1 != 7)
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
u32 *destreg, *srcreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
@ -286,7 +289,7 @@ void x86emuOp_genop_word_RM_R(u8 op1)
TRACE_AND_STEP();
*destreg = genop_long_operation[op1](*destreg, *srcreg);
} else {
u16 *destreg,*srcreg;
u16 *destreg, *srcreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
@ -1332,9 +1335,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
imm = fetch_byte_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_byte_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
*destreg = (*genop_byte_operation[rh]) (*destreg, imm);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
@ -1423,29 +1424,23 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 destval,imm;
u32 *destreg, imm;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
imm = fetch_long_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_long_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
*destreg = (*genop_long_operation[rh]) (*destreg, imm);
} else {
u16 *destreg;
u16 destval,imm;
u16 *destreg, imm;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
imm = fetch_word_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_word_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
*destreg = (*genop_word_operation[rh]) (*destreg, imm);
}
}
DECODE_CLEAR_SEGOVR();
@ -1523,9 +1518,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
imm = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_byte_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
*destreg = (*genop_byte_operation[rh]) (*destreg, imm);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
@ -1611,27 +1604,21 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 destval,imm;
u32 *destreg, imm;
destreg = DECODE_RM_LONG_REGISTER(rl);
imm = (s8) fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_long_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
*destreg = (*genop_long_operation[rh]) (*destreg, imm);
} else {
u16 *destreg;
u16 destval,imm;
u16 *destreg, imm;
destreg = DECODE_RM_WORD_REGISTER(rl);
imm = (s8) fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_word_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
*destreg = (*genop_word_operation[rh]) (*destreg, imm);
}
}
DECODE_CLEAR_SEGOVR();

2
src/devices/emulator/x86emu/ops2.c
View File

@ -61,7 +61,7 @@ void x86emuOp2_illegal_op(
END_OF_INSTR();
}
#define xorl(a,b) ((a) && !(b)) || (!(a) && (b))
#define xorl(a,b) (((a) && !(b)) || (!(a) && (b)))
/****************************************************************************
REMARKS:

2
src/devices/emulator/x86emu/prim_ops.c
View File

@ -1921,7 +1921,7 @@ Implements the IMUL instruction and side effects.
void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
{
#ifdef __HAS_LONG_LONG__
s64 res = (s32)d * (s32)s;
s64 res = (s64)d * (s64)s;
*res_lo = (u32)res;
*res_hi = (u32)(res >> 32);

6
src/devices/pci_rom.c
View File

@ -53,7 +53,7 @@ struct rom_header * pci_rom_probe(struct device *dev)
if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
printk_err("Class Code mismatch ROM %08x, dev %08x\n",
(rom_data->class_hi << 8) | rom_data->class_lo, dev->class);
// return NULL;
//return NULL;
}
return rom_header;
@ -62,8 +62,8 @@ struct rom_header * pci_rom_probe(struct device *dev)
static void *pci_ram_image_start = PCI_RAM_IMAGE_START;
#if CONFIG_CONSOLE_VGA == 1
int vga_inited = 0; // it will be used by vga_console
extern device_t vga_pri; // The only VGA
int vga_inited = 0; // used by vga_console.c
extern device_t vga_pri; // the primary vga device, defined in device.c
#endif
struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header)

51
src/mainboard/arima/hdama/Config.lb
View File

@ -129,26 +129,39 @@ config chip.h
# config for arima/hdama
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
device pci 0.0 on end # PCIX bridge
device pci 0.1 on end # IOAPIC
device pci 1.0 on end # PCIX bridge
device pci 1.1 on end # IOAPIC
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# this "device pci 0.0" is the parent of the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 off end
device pci 1.0 off end
device pci 0.0 on end # USB0
device pci 0.1 on end # USB1
device pci 0.2 off end # USB 2.0
device pci 1.0 off end # LAN
chip drivers/pci/onboard
device pci 6.0 on end # ATI Rage XL
register "rom_address" = "0xfff80000"
end
end
# LPC bridge
device pci 1.0 on
chip superio/NSC/pc87360
device pnp 2e.0 off # Floppy
@ -181,9 +194,9 @@ chip northbridge/amd/amdk8/root_complex
device pnp 2e.a off end # WDT
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on
device pci 1.1 on end # IDE
device pci 1.2 on end # SMBus 2.0
device pci 1.3 on # System Management
chip drivers/generic/generic
#phillips pca9545 smbus mux
device i2c 70 on
@ -221,8 +234,8 @@ chip northbridge/amd/amdk8/root_complex
device i2c 57 on end
end
end
device pci 1.5 off end
device pci 1.6 on end
device pci 1.5 off end # AC97 Audio
device pci 1.6 on end # AC97 Modem
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
@ -233,7 +246,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
end # chip northbridge/amd/amdk8
chip northbridge/amd/amdk8
device pci 19.0 on end
device pci 19.0 on end
@ -243,13 +256,5 @@ chip northbridge/amd/amdk8/root_complex
device pci 19.3 on end
end
end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
chip cpu/amd/socket_940
device apic 1 on end
end
end
end

6
src/mainboard/arima/hdama/Options.lb
View File

@ -50,6 +50,8 @@ uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
###
### Build options
@ -119,6 +121,10 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
##
default CONFIG_IOAPIC=1
#VGA
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
##
## Clean up the motherboard id strings
##

9
src/mainboard/ibm/e325/auto.c
View File

@ -158,16 +158,21 @@ static void main(unsigned long bist)
};
int needs_reset;
unsigned nodeid;
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
/* Has this cpu already booted? */
if (cpu_init_detected()) {
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets();
distinguish_cpu_resets(nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}

5
src/mainboard/ibm/e325/failover.c
View File

@ -13,11 +13,14 @@
static unsigned long main(unsigned long bist)
{
unsigned nodeid;
/* Make cerain my local apic is useable */
enable_lapic();
nodeid = lapicid() & 0xf;
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (cpu_init_detected(nodeid)) {
if (last_boot_normal()) {
goto normal_image;
} else {

31
src/mainboard/via/epia/Config.lb
View File

@ -126,20 +126,18 @@ config chip.h
chip northbridge/via/vt8601
device pci_domain 0 on
device pci 0.0 on
device pci 0.0 on end # Northbridge
device pci 0.1 on # AGP bridge
# chip drivers/pci/onboard # Integrated VGA
# device pci 0.0 on end
# register "rom_adress" = "0xfff80000"
# end
end
chip southbridge/via/vt8231
register "enable_usb" = "0"
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
device pci 11.0 on # Southbridge
device pci 11.1 on end # Ide
device pci 11.2 off end # Usb
device pci 11.3 off end # Usb
device pci 11.4 off end # ACPI
device pci 11.5 off end # Audio
device pci 11.6 on # Com
device pci 11.0 on # Southbrdge
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
@ -164,6 +162,8 @@ chip northbridge/via/vt8601
irq 0x70 = 1
irq 0x72 = 12
end
register "com1" = "{1}"
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
@ -172,14 +172,17 @@ chip northbridge/via/vt8601
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
register "com1" = "{1}"
end
end
device pci 11.1 on end # Ide
device pci 11.2 off end # Usb port 0-1
device pci 11.3 off end # Usb port 2-3
device pci 11.4 off end # ACPI
device pci 11.5 off end # AC97 Audio
device pci 11.6 on end # AC97 Modem
device pci 12.0 on end # Ethernet
end
end
end
end
chip cpu/via/model_centaur
end
end

19
src/mainboard/via/epia/Options.lb
View File

@ -1,3 +1,10 @@
uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_CHIP_NAME
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
@ -40,6 +47,18 @@ uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=19200
# Select the serial console base port
default TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_CHIP_NAME=1
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024

24
src/mainboard/via/epia/auto.c
View File

@ -2,9 +2,6 @@
#include <stdint.h>
#include <device/pci_def.h>
#if 0
#include <cpu/x86/lapic.h>
#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
@ -21,7 +18,7 @@
void udelay(int usecs)
{
int i;
for(i = 0; i < usecs; i++)
for (i = 0; i < usecs; i++)
outb(i&0xff, 0x80);
}
@ -30,18 +27,8 @@ void udelay(int usecs)
#include "debug.c"
#include "southbridge/via/vt8231/vt8231_early_smbus.c"
#include "southbridge/via/vt8231/vt8231_early_serial.c"
static void memreset_setup(void)
{
}
/*
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
*/
static inline int spd_read_byte(unsigned device, unsigned address)
{
unsigned char c;
@ -49,8 +36,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return c;
}
#include "northbridge/via/vt8601/raminit.c"
/*
#include "sdram/generic_sdram.c"
@ -66,6 +51,7 @@ static void enable_mainboard_devices(void)
if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n");
}
pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff);
#if 0
@ -87,9 +73,9 @@ static void enable_mainboard_devices(void)
static void enable_shadow_ram(void)
{
device_t dev = 0; /* no need to look up 0:0.0 */
device_t dev = 0;
unsigned char shadowreg;
/* dev 0 for southbridge */
shadowreg = pci_read_config8(dev, 0x63);
/* 0xf0000-0xfffff */
shadowreg |= 0x30;
@ -113,8 +99,8 @@ static void main(unsigned long bist)
enable_mainboard_devices();
enable_smbus();
enable_shadow_ram();
/*
memreset_setup();
this is way more generic than we need.
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
*/

4
src/northbridge/via/vt8601/northbridge.c
View File

@ -29,8 +29,6 @@ static void northbridge_init(device_t dev)
pci_write_config8(dev, 0x76, 0x52);
}
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
@ -46,8 +44,6 @@ static struct pci_driver northbridge_driver __pci_driver = {
.device = 0x0601, /* 0x8601 is the AGP bridge? */
};
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)

135
src/northbridge/via/vt8601/raminit.c
View File

@ -53,8 +53,8 @@ void dimms_read(unsigned long x)
unsigned long eax;
volatile unsigned long y;
eax = x;
for(c = 0; c < 6; c++) {
y = * (volatile unsigned long *) eax;
for (c = 0; c < 6; c++) {
y = *(volatile unsigned long *) eax;
eax += 0x10000000;
}
}
@ -63,14 +63,12 @@ void dimms_write(int x)
{
uint8_t c;
unsigned long eax = x;
for(c = 0; c < 6; c++) {
for (c = 0; c < 6; c++) {
*(volatile unsigned long *) eax = 0;
eax += 0x10000000;
}
}
#ifdef DEBUG_SETNORTHB
void setnorthb(device_t north, uint8_t reg, uint8_t val)
{
@ -85,15 +83,14 @@ void setnorthb(device_t north, uint8_t reg, uint8_t val)
#define setnorthb pci_write_config8
#endif
void
dumpnorth(device_t north)
void dumpnorth(device_t north)
{
unsigned int r, c;
for(r = 0; ; r += 16) {
for (r = 0;; r += 16) {
print_debug_hex8(r);
print_debug(":");
for(c = 0; c < 16; c++) {
print_debug_hex8(pci_read_config8(north, r+c));
for (c = 0; c < 16; c++) {
print_debug_hex8(pci_read_config8(north, r + c));
print_debug(" ");
}
print_debug("\r\n");
@ -104,12 +101,10 @@ dumpnorth(device_t north)
static void sdram_set_registers(const struct mem_controller *ctrl)
{
device_t north = (device_t) 0;
device_t north = (device_t) PCI_DEV(0, 0, 0);
uint8_t c, r;
print_err("vt8601 init starting\r\n");
north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
north = 0;
print_debug_hex32(north);
print_debug(" is the north\n");
print_debug_hex16(pci_read_config16(north, 0));
@ -120,72 +115,75 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
/* All we are doing now is setting initial known-good values that will
* be revised later as we read SPD
*/
// memory clk enable. We are not using ECC
pci_write_config8(north,0x78, 0x01);
pci_write_config8(north, 0x78, 0x01);
print_debug_hex8(pci_read_config8(north, 0x78));
// dram control, see the book.
#if DIMM_PC133
pci_write_config8(north,0x68, 0x52);
pci_write_config8(north, 0x68, 0x52);
#else
pci_write_config8(north,0x68, 0x42);
pci_write_config8(north, 0x68, 0x42);
#endif
// dram control, see the book.
pci_write_config8(north,0x6B, 0x0c);
pci_write_config8(north, 0x6B, 0x0c);
// Initial setting, 256MB in each bank, will be rewritten later.
pci_write_config8(north,0x5A, 0x20);
pci_write_config8(north, 0x5A, 0x20);
print_debug_hex8(pci_read_config8(north, 0x5a));
pci_write_config8(north,0x5B, 0x40);
pci_write_config8(north,0x5C, 0x60);
pci_write_config8(north,0x5D, 0x80);
pci_write_config8(north,0x5E, 0xA0);
pci_write_config8(north,0x5F, 0xC0);
pci_write_config8(north, 0x5B, 0x40);
pci_write_config8(north, 0x5C, 0x60);
pci_write_config8(north, 0x5D, 0x80);
pci_write_config8(north, 0x5E, 0xA0);
pci_write_config8(north, 0x5F, 0xC0);
// It seems we have to take care of these 2 registers as if
// they are bank 6 and 7.
pci_write_config8(north,0x56, 0xC0);
pci_write_config8(north,0x57, 0xC0);
pci_write_config8(north, 0x56, 0xC0);
pci_write_config8(north, 0x57, 0xC0);
// SDRAM in all banks
pci_write_config8(north,0x60, 0x3F);
pci_write_config8(north, 0x60, 0x3F);
// DRAM timing. I'm suspicious of this
// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
// ras precharge 4T, RAS pulse 5T
// cas2 is 0xd6, cas3 is 0xe6
// we're also backing off write pulse width to 2T, so result is 0xee
#if DIMM_CL2
pci_write_config8(north,0x64, 0xd4);
pci_write_config8(north,0x65, 0xd4);
pci_write_config8(north,0x66, 0xd4);
pci_write_config8(north, 0x64, 0xd4);
pci_write_config8(north, 0x65, 0xd4);
pci_write_config8(north, 0x66, 0xd4);
#else // CL=3
pci_write_config8(north,0x64, 0xe4);
pci_write_config8(north,0x65, 0xe4);
pci_write_config8(north,0x66, 0xe4);
pci_write_config8(north, 0x64, 0xe4);
pci_write_config8(north, 0x65, 0xe4);
pci_write_config8(north, 0x66, 0xe4);
#endif
// dram frequency select.
// enable 4K pages for 64M dram.
#if DIMM_PC133
pci_write_config8(north,0x69, 0x3c);
pci_write_config8(north, 0x69, 0x3c);
#else
pci_write_config8(north,0x69, 0xac);
pci_write_config8(north, 0x69, 0xac);
#endif
/* IMPORTANT -- disable refresh counter */
// refresh counter, disabled.
pci_write_config8(north,0x6A, 0x00);
pci_write_config8(north, 0x6A, 0x00);
// clkenable configuration. kevinh FIXME - add precharge
pci_write_config8(north,0x6C, 0x00);
pci_write_config8(north, 0x6C, 0x00);
// dram read latch delay of 1 ns, MD drive 8 mA,
// high drive strength on MA[2: 13], we#, cas#, ras#
// As per Cindy Lee, set to 0x37, not 0x57
pci_write_config8(north,0x6D, 0x7f);
pci_write_config8(north, 0x6D, 0x7f);
}
/* slot is the dram slot. Return size of side0 in lower 16-bit,
* side1 in upper 16-bit, in units of 8MB */
static unsigned long
spd_module_size(unsigned char slot)
static unsigned long spd_module_size(unsigned char slot)
{
/* for all the DRAMS, see if they are there and get the size of each
* module. This is just a very early first cut at sizing.
@ -195,6 +193,7 @@ spd_module_size(unsigned char slot)
unsigned int value = 0;
/* unsigned int module = ((0x50 + slot) << 1) + 1; */
unsigned int module = 0x50 + slot;
/* is the module there? if byte 2 is not 4, then we'll assume it
* is useless.
*/
@ -207,9 +206,11 @@ spd_module_size(unsigned char slot)
print_info(" is SDRAM ");
banks = smbus_read_byte(module, 17);
/* we're going to assume symmetric banks. Sorry. */
cols = smbus_read_byte(module, 4) & 0xf;
rows = smbus_read_byte(module, 3) & 0xf;
/* grand total. You have rows+cols addressing, * times of banks, times
* width of data in bytes */
/* Width is assumed to be 64 bits == 8 bytes */
@ -229,10 +230,8 @@ spd_module_size(unsigned char slot)
}
static int
spd_num_chips(unsigned char slot)
static int spd_num_chips(unsigned char slot)
{
/* unsigned int module = ((0x50 + slot) << 1) + 1; */
unsigned int module = 0x50 + slot;
unsigned int width;
@ -249,10 +248,10 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
unsigned char timing = 0xe4;
/* read Trp */
val = smbus_read_byte(0x50, 27);
if (val < 2*T133)
if (val < 2 * T133)
Trp = 1;
val = smbus_read_byte(0x50, 30);
if (val < 5*T133)
if (val < 5 * T133)
Tras = 0;
val = smbus_read_byte(0x50, 18);
if (val < 8)
@ -262,7 +261,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
print_debug_hex8(val); print_debug(" is the computed timing\n");
print_debug_hex8(val);
print_debug(" is the computed timing\n");
/* don't set it. Experience shows that this screwy chipset should just
* be run with the most conservative timing.
* pci_write_config8(0, 0x64, val);
@ -274,8 +274,8 @@ static void set_ma_mapping(device_t north, int slot, int type)
unsigned char reg, val;
int shift;
reg = 0x58 + slot/2;
if (slot%2 >= 1)
reg = 0x58 + slot / 2;
if (slot % 2 >= 1)
shift = 0;
else
shift = 4;
@ -295,29 +295,30 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
};
device_t north = 0;
uint32_t size, base, slot, ma;
/* begin to initialize*/
/* begin to initialize */
// I forget why we need this, but we do
dimms_write(0xa55a5aa5);
/* set NOP*/
pci_write_config8(north,0x6C, 0x01);
/* set NOP */
pci_write_config8(north, 0x6C, 0x01);
print_debug("NOP\r\n");
/* wait 200us*/
/* wait 200us */
// You need to do the memory reference. That causes the nop cycle.
dimms_read(0);
udelay(400);
print_debug("PRECHARGE\r\n");
/* set precharge */
pci_write_config8(north,0x6C, 0x02);
pci_write_config8(north, 0x6C, 0x02);
print_debug("DUMMY READS\r\n");
/* dummy reads*/
/* dummy reads */
dimms_read(0);
udelay(200);
print_debug("CBR\r\n");
/* set CBR*/
pci_write_config8(north,0x6C, 0x04);
/* set CBR */
pci_write_config8(north, 0x6C, 0x04);
/* do 8 reads and wait >100us between each - from via*/
/* do 8 reads and wait >100us between each - from via */
dimms_read(0);
udelay(200);
dimms_read(0);
@ -335,8 +336,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dimms_read(0);
udelay(200);
print_debug("MRS\r\n");
/* set MRS*/
pci_write_config8(north,0x6c, 0x03);
/* set MRS */
pci_write_config8(north, 0x6c, 0x03);
#if DIMM_CL2
dimms_read(0x150);
#else // CL=3
@ -345,7 +346,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
udelay(200);
print_debug("NORMAL\r\n");
/* set to normal mode */
pci_write_config8(north,0x6C, 0x08);
pci_write_config8(north, 0x6C, 0x08);
dimms_write(0x55aa55aa);
dimms_read(0);
@ -353,25 +354,25 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("set ref. rate\r\n");
// Set the refresh rate.
#if DIMM_PC133
pci_write_config8(north,0x6A, 0x86);
pci_write_config8(north, 0x6A, 0x86);
#else
pci_write_config8(north,0x6A, 0x65);
pci_write_config8(north, 0x6A, 0x65);
#endif
print_debug("enable multi-page open\r\n");
// enable multi-page open
pci_write_config8(north,0x6B, 0x0d);
pci_write_config8(north, 0x6B, 0x0d);
base = 0;
for(slot = 0; slot < 4; slot++) {
for (slot = 0; slot < 4; slot++) {
size = spd_module_size(slot);
/* side 0 */
base += size & 0xffff;
pci_write_config8(north, ramregs[2*slot], base);
pci_write_config8(north, ramregs[2 * slot], base);
/* side 1 */
base += size >> 16;
if (base > 0xff)
base = 0xff;
pci_write_config8(north, ramregs[2*slot + 1], base);
pci_write_config8(north, ramregs[2 * slot + 1], base);
if (!size)
continue;
@ -385,7 +386,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug(" is the chip size\r\n");
if (size < 64)
ma = 0;
if (size < 256)
else if (size < 256)
ma = 8;
else
ma = 0xe;

8
src/southbridge/via/vt8231/Config.lb
View File

@ -1,2 +1,8 @@
config chip.h
object vt8231.o
driver vt8231.o
driver vt8231_lpc.o
driver vt8231_acpi.o
driver vt8231_ide.o
driver vt8231_nic.o
#driver vt8231_usb.o

10
src/southbridge/via/vt8231/chip.h
View File

@ -4,18 +4,10 @@
extern struct chip_operations southbridge_via_vt8231_ops;
struct southbridge_via_vt8231_config {
/* PCI function enables */
/* i.e. so that pci scan bus will find them. */
/* I am putting in IDE as an example but obviously this needs
* to be more complete!
*/
int enable_ide;
/* enables of functions of devices */
int enable_usb;
/* enables of Non-PCI devices */
int enable_native_ide;
int enable_com_ports;
int enable_keyboard;
int enable_nvram;
};
#endif /* _SOUTHBRIDGE_VIA_VT8231 */

428
src/southbridge/via/vt8231/vt8231.c
View File

@ -1,281 +1,45 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#include <pc80/keyboard.h>
#include "vt8231.h"
#include "chip.h"
void pc_keyboard_init(void);
/* Base 8231 controller */
static device_t lpc_dev;
void hard_reset(void)
{
printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
}
static void usb_on(int enable)
{
unsigned char regval;
/* Base 8231 controller */
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* USB controller 1 */
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
/* USB controller 2 */
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
/* enable USB1 */
if(dev2) {
if (enable) {
pci_write_config8(dev2, 0x3c, 0x05);
pci_write_config8(dev2, 0x04, 0x07);
} else {
pci_write_config8(dev2, 0x3c, 0x00);
pci_write_config8(dev2, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x10);
else
regval |= 0x10;
pci_write_config8(dev0, 0x50, regval);
}
/* enable USB2 */
if(dev3) {
if (enable) {
pci_write_config8(dev3, 0x3c, 0x05);
pci_write_config8(dev3, 0x04, 0x07);
} else {
pci_write_config8(dev3, 0x3c, 0x00);
pci_write_config8(dev3, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x20);
else
regval |= 0x20;
pci_write_config8(dev0, 0x50, regval);
}
}
static void keyboard_on(void)
{
unsigned char regval;
/* Base 8231 controller */
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* kevinh/Ispiri - update entire function to use
new pci_write_config8 */
if (dev0) {
regval = pci_read_config8(dev0, 0x51);
if (lpc_dev) {
regval = pci_read_config8(lpc_dev, 0x51);
regval |= 0x0f;
pci_write_config8(dev0, 0x51, regval);
pci_write_config8(lpc_dev, 0x51, regval);
}
init_pc_keyboard(0x60, 0x64, 0);
}
static void nvram_on(void)
static void com_port_on(void)
{
/*
* the VIA 8231 South has a very different nvram setup than the
* piix4e ...
* turn on ProMedia nvram.
* TO DO: use the PciWriteByte function here.
*/
/*
* kevinh/Ispiri - I don't think this is the correct address/value
* intel_conf_writeb(0x80008841, 0xFF);
*/
}
/*
* Enable the ethernet device and turn off stepping (because it is integrated
* inside the southbridge)
*/
static void ethernet_fixup()
{
device_t edev;
uint8_t byte;
printk_info("Ethernet fixup\n");
edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
if (edev) {
printk_debug("Configuring VIA LAN\n");
/* We don't need stepping - though the device supports it */
byte = pci_read_config8(edev, PCI_COMMAND);
byte &= ~PCI_COMMAND_WAIT;
pci_write_config8(edev, PCI_COMMAND, byte);
} else {
printk_debug("VIA LAN not found\n");
}
}
/* we need to do things in this function so that PCI scan will find
* them. One problem here is that we can't use ANY of the new device
* stuff. This work here precedes all that.
* Fundamental problem with linuxbios V2 architecture.
* You can't do pci control in the C code without having done a PCI scan.
* But in some cases you need to to pci control in the c code before doing
* a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
* that has functions with the same name but different type signatures
* (e.g. device_t). This needs to get fixed. We need low-level pci scans
* in the C code.
*/
static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf)
{
/*
unsigned long busdevfn = 0x8000;
if (conf->enable_ide) {
printk_debug("%s: enabling IDE function\n", __FUNCTION__);
}
*/
}
/* PIRQ init
*/
void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
/*
Our IDSEL mappings are as follows
PCI slot is AD31 (device 15) (00:14.0)
Southbridge is AD28 (device 12) (00:11.0)
*/
static void pci_routing_fixup(struct device *dev)
{
printk_info("%s: dev is %p\n", __FUNCTION__, dev);
if (dev) {
/* initialize PCI interupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ11
PINTB = IRQ5
PINTC = IRQ10
PINTD = IRQ12
*/
pci_write_config8(dev, 0x55, 0xb0);
pci_write_config8(dev, 0x56, 0xa5);
pci_write_config8(dev, 0x57, 0xc0);
}
// Standard southbridge components
printk_info("setting southbridge\n");
pci_assign_irqs(0, 0x11, southbridgeIrqs);
// Ethernet built into southbridge
printk_info("setting ethernet\n");
pci_assign_irqs(0, 0x12, enetIrqs);
// PCI slot
printk_info("setting pci slot\n");
pci_assign_irqs(0, 0x14, slotIrqs);
printk_info("%s: DONE\n", __FUNCTION__);
}
void
dump_south(void)
{
device_t dev0;
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
int i,j;
for(i = 0; i < 256; i += 16) {
printk_debug("0x%x: ", i);
for(j = 0; j < 16; j++) {
printk_debug("%02x ", pci_read_config8(dev0, i+j));
}
printk_debug("\n");
}
}
static void vt8231_init(struct southbridge_via_vt8231_config *conf)
{
unsigned char enables;
device_t dev0;
device_t dev1;
device_t devpwr;
// to do: use the pcibios_find function here, instead of
// hard coding the devfn.
// done - kevinh/Ispiri
printk_debug("vt8231 init\n");
/* Base 8231 controller */
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* IDE controller */
dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
/* Power management controller */
devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0);
// enable the internal I/O decode
enables = pci_read_config8(dev0, 0x6C);
enables |= 0x80;
pci_write_config8(dev0, 0x6C, enables);
// Map 4MB of FLASH into the address space
pci_write_config8(dev0, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev0, 0x40);
pci_write_config8(dev0, 0x40, enables);
// Set 0x42 to 0xf0 to match Award bios
enables = pci_read_config8(dev0, 0x42);
enables |= 0xf0;
pci_write_config8(dev0, 0x42, enables);
// Set bit 3 of 0x4a, to match award (dummy pci request)
enables = pci_read_config8(dev0, 0x4a);
enables |= 0x08;
pci_write_config8(dev0, 0x4a, enables);
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
enables = pci_read_config8(dev0, 0x4f);
enables |= 0x08;
pci_write_config8(dev0, 0x4f, enables);
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev0, 0x58, 0x03);
// enable the ethernet/RTC
if(dev0) {
enables = pci_read_config8(dev0, 0x51);
enables |= 0x18;
pci_write_config8(dev0, 0x51, enables);
}
#if 0
// enable com1 and com2.
if (conf->enable_com_ports) {
enables = pci_read_config8(dev0, 0x6e);
enables = pci_read_config8(dev, 0x6e);
/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
* is enable com port a as com1 kevinh/Ispiri - Old code
* thought 0x01 would make it com1, that was wrong enables =
* 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e,
* 0x80 | 0x10 | 0x8 ; pci_write_config8(dev, 0x6e,
* enables); // note: this is also a redo of some port of
* assembly, but we want everything up.
*/
@ -283,159 +47,27 @@ static void vt8231_init(struct southbridge_via_vt8231_config *conf)
/* set com1 to 115 kbaud not clear how to do this yet.
* forget it; done in assembly.
*/
}
// enable IDE, since Linux won't do it.
// First do some more things to devfn (17,0)
// note: this should already be cleared, according to the book.
enables = pci_read_config8(dev0, 0x50);
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
enables &= ~8; // need manifest constant here!
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
pci_write_config8(dev0, 0x50, enables);
// set default interrupt values (IDE)
enables = pci_read_config8(dev0, 0x4c);
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
// clear out whatever was there.
enables &= ~0xf;
enables |= 4;
printk_debug("setting reg. 4c to 0x%x\n", enables);
pci_write_config8(dev0, 0x4c, enables);
// set up the serial port interrupts.
// com2 to 3, com1 to 4
pci_write_config8(dev0, 0x46, 0x04);
pci_write_config8(dev0, 0x47, 0x03);
pci_write_config8(dev0, 0x6e, 0x98);
//
// Power management setup
//
// Set ACPI base address to IO 0x4000
pci_write_config32(devpwr, 0x48, 0x4001);
// Enable ACPI access (and setup like award)
pci_write_config8(devpwr, 0x41, 0x84);
// Set hardware monitor base address to IO 0x6000
pci_write_config32(devpwr, 0x70, 0x6001);
// Enable hardware monitor (and setup like award)
pci_write_config8(devpwr, 0x74, 0x01);
// set IO base address to 0x5000
pci_write_config32(devpwr, 0x90, 0x5001);
// Enable SMBus
pci_write_config8(devpwr, 0xd2, 0x01);
//
// IDE setup
//
if (! conf->enable_native_ide) {
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
enables = pci_read_config8(dev1, 0x42);
printk_debug("enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatability mode
pci_write_config8(dev1, 0x42, enables);
enables = pci_read_config8(dev1, 0x42);
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
}
enables = pci_read_config8(dev1, 0x40);
printk_debug("enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pci_write_config8(dev1, 0x40, enables);
enables = pci_read_config8(dev1, 0x40);
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
enables = pci_read_config8(dev1, 0x41);
enables |= 0xf0;
pci_write_config8(dev1, 0x41, enables);
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev1, 0x43);
enables &= ~0x0f;
enables |= 0x05;
pci_write_config8(dev1, 0x43, enables);
// PIO read prefetch counter (cause award does it)
pci_write_config8(dev1, 0x44, 0x18);
// Use memory read multiple
pci_write_config8(dev1, 0x45, 0x1c);
// address decoding.
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev1, 0x9);
printk_debug("enables in reg 0x9 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
// cf/cg silicon needs an 'f' here.
enables |= 0xf;
} else {
enables &= ~0x5;
}
pci_write_config8(dev1, 0x9, enables);
enables = pci_read_config8(dev1, 0x9);
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
// standard bios sets master bit.
enables = pci_read_config8(dev1, 0x4);
printk_debug("command in reg 0x4 0x%x\n", enables);
enables |= 7;
// No need for stepping - kevinh@ispiri.com
enables &= ~0x80;
pci_write_config8(dev1, 0x4, enables);
enables = pci_read_config8(dev1, 0x4);
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
if (! conf->enable_native_ide) {
// Use compatability mode - per award bios
pci_write_config32(dev1, 0x10, 0x0);
pci_write_config32(dev1, 0x14, 0x0);
pci_write_config32(dev1, 0x18, 0x0);
pci_write_config32(dev1, 0x1c, 0x0);
// Force interrupts to use compat mode - just like Award bios
pci_write_config8(dev1, 0x3d, 00);
pci_write_config8(dev1, 0x3c, 0xff);
}
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev0, 0x40, 0x54);
ethernet_fixup();
// Start the rtc
rtc_init(0);
#endif
}
static void southbridge_init(struct device *dev) {
vt8231_init(dev->chip_info);
pci_routing_fixup(dev);
}
struct device_operations vt8231_dev_ops = {
.init = &southbridge_init,
};
static void southbridge_enable(struct device *dev)
/* FixME: to be removed ? */
static void vt8231_enable(struct device *dev)
{
dev->ops = &vt8231_dev_ops;
struct southbridge_via_vt8231_config *conf = dev->chip_info;
if (!lpc_dev) {
/* the first time called, enable devices not on PCI bus
* FIXME: is that device struct there yet? */
lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8231, 0);
if (conf->enable_keyboard)
keyboard_on();
if (conf->enable_com_ports)
com_port_on();
}
}
struct chip_operations southbridge_via_vt8231_ops = {
CHIP_NAME("VIA vt8231")
.enable_dev = southbridge_enable,
.enable_dev = vt8231_enable,
};

64
src/southbridge/via/vt8231/vt8231_early_smbus.c
View File

@ -27,14 +27,13 @@ static void enable_smbus(void)
device_t dev;
unsigned char c;
/* Power management controller */
dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n");
}
// set IO base address to SMBUS_IO_BASE
pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
// Enable SMBus
c = pci_read_config8(dev, 0xd2);
@ -43,7 +42,7 @@ static void enable_smbus(void)
/* make it work for I/O ...
*/
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
c = pci_read_config8(dev, 4);
c |= 1;
pci_write_config8(dev, 4, c);
@ -70,8 +69,8 @@ static int smbus_wait_until_active(void)
if ((val & 1)) {
break;
}
} while(--loops);
return loops?0:-4;
} while (--loops);
return loops ? 0 : -4;
}
static int smbus_wait_until_ready(void)
@ -85,12 +84,11 @@ static int smbus_wait_until_ready(void)
if ((val & 1) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
SMBUS_IO_BASE + SMBHSTSTAT);
if (loops == (SMBUS_TIMEOUT / 2)) {
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
} while(--loops);
return loops?0:-2;
} while (--loops);
return loops ? 0 : -2;
}
static int smbus_wait_until_done(void)
@ -102,11 +100,11 @@ static int smbus_wait_until_done(void)
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ( (val & 1) == 0) {
if ((val & 1) == 0) {
break;
}
} while(--loops);
return loops?0:-3;
} while (--loops);
return loops ? 0 : -3;
}
void smbus_reset(void)
@ -118,7 +116,7 @@ void smbus_reset(void)
smbus_wait_until_ready();
print_debug("After reset status ");
print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
print_debug("\r\n");
}
@ -158,7 +156,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
if (smbus_wait_until_ready() < 0) {
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
if ( smbus_wait_until_ready() < 0 ) {
if (smbus_wait_until_ready() < 0) {
return -2;
}
}
@ -171,12 +169,12 @@ static int smbus_read_byte(unsigned device, unsigned address)
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte...*/
/* clear the data byte... */
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start a byte read, with interrupts disabled */
@ -192,7 +190,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
}
/* Ignore the Host Busy & Command Complete ? */
global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1<<1)|(1<<0));
global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0));
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
@ -206,8 +204,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
#if 0
/* SMBus routines borrowed from VIA's Trident Driver */
/* this works, so I am not going to touch it for now -- rgm */
static unsigned char smbus_read_byte(unsigned char devAdr,
unsigned char bIndex)
static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex)
{
unsigned int i;
unsigned char bData;
@ -217,28 +214,28 @@ static unsigned char smbus_read_byte(unsigned char devAdr,
outb(0xff, SMBUS_IO_BASE);
/* check SMBUS ready */
for ( i = 0; i < SMBUS_TIMEOUT; i++ )
if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
for (i = 0; i < SMBUS_TIMEOUT; i++)
if ((inb(SMBUS_IO_BASE) & 0x01) == 0)
break;
/* set host command */
outb(bIndex, SMBUS_IO_BASE+3);
outb(bIndex, SMBUS_IO_BASE + 3);
/* set slave address */
outb(devAdr | 0x01, SMBUS_IO_BASE+4);
outb(devAdr | 0x01, SMBUS_IO_BASE + 4);
/* start */
outb(0x48, SMBUS_IO_BASE+2);
outb(0x48, SMBUS_IO_BASE + 2);
/* SMBUS Wait Ready */
for ( i = 0; i < SMBUS_TIMEOUT; i++ )
if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 )
for (i = 0; i < SMBUS_TIMEOUT; i++)
if (((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0)
break;
if ((sts & ~3) != 0) {
smbus_print_error(sts);
return 0;
}
bData=inb(SMBUS_IO_BASE+5);
bData = inb(SMBUS_IO_BASE + 5);
return bData;
@ -265,18 +262,16 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
SMBUS_IO_BASE + SMBHSTCTL);
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte...*/
/* clear the data byte... */
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start the command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
SMBUS_IO_BASE + SMBHSTCTL);
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for transaction completion */
smbus_wait_until_done();
@ -296,4 +291,3 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
#endif

12
targets/arima/hdama/Config.lb
View File

@ -6,20 +6,22 @@
target hdama
mainboard arima/hdama
option ROM_SIZE=487424
# Arima hdama
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10400
option ROM_IMAGE_SIZE=0x16000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
payload /usr/share/etherboot/5.2.1eb1-lnxi-lb/tg3--ide_disk.zelf
payload /home/ollie/work/filo-0.4.1/filo.elf
# payload /etc/hosts
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10400
option ROM_IMAGE_SIZE=0x16000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
payload /usr/share/etherboot/5.2.1eb1-lnxi-lb/tg3--ide_disk.zelf
# use this to test a build if you don't have the etherboot
payload /home/ollie/work/filo-0.4.1/filo.elf
# payload /etc/hosts
end

88
targets/ibm/e325/Config.lb
View File

@ -1,87 +1,9 @@
# the IBM E325
# This will make a target directory of ./e325
loadoptions
target e325
uses ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses CONFIG_SERIAL_POST
uses NO_POST
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
uses FALLBACK_SIZE
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_HARD_RESET
uses i586
uses i686
uses INTEL_PPRO_MTRR
uses HEAP_SIZE
uses IRQ_SLOT_COUNT
uses k7
uses k8
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses CONFIG_SMP
uses CONFIG_MAX_CPUS
uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses _ROMBASE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
uses STACK_SIZE
uses USE_FALLBACK_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses MAINBOARD
uses CONFIG_CHIP_CONFIGURE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses LINUXBIOS_EXTRA_VERSION
option CONFIG_CHIP_CONFIGURE=1
option MAXIMUM_CONSOLE_LOGLEVEL=9
option DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_CONSOLE_SERIAL8250=1
option CONFIG_SERIAL_POST=1
option NO_POST=0
option CPU_FIXUP=1
option CONFIG_UDELAY_TSC=0
option i686=1
option i586=1
option INTEL_PPRO_MTRR=1
option k7=1
option k8=1
option ROM_SIZE=1048576
option HAVE_OPTION_TABLE=1
option CONFIG_ROM_STREAM=1
option HAVE_FALLBACK_BOOT=1
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072
## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00004000
mainboard ibm/e325
#
###
@ -95,16 +17,16 @@ romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
mainboard ibm/e325
payload ../../filo.elf
# payload ../../filo.elf
payload /home/ollie/work/filo-0.4.1/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
mainboard ibm/e325
payload ../../filo.elf
# payload ../../filo.elf
payload /home/ollie/work/filo-0.4.1/filo.elf
# use this to test a build if you don't have the etherboot
# payload /etc/hosts
end

13
targets/via/epia/Config.lb
View File

@ -3,6 +3,12 @@
target epia
mainboard via/epia
## Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=9
## At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=9
#
# Via Epia
romimage "normal"
@ -11,7 +17,9 @@ romimage "normal"
option LINUXBIOS_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
# payload ../../../../../lnxieepro100.ebi
payload /home/ollie/work/filo-0.4.1/filo.elf
end
romimage "fallback"
@ -20,7 +28,8 @@ romimage "fallback"
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi
# payload ../../../../../lnxieepro100.ebi
payload /home/ollie/work/filo-0.4.1/filo.elf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"