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soc/intel/cannonlake: Add microcode support 

Microcode needs to be loaded prior to FSP initialization.

Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20484
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2017-07-06 15:27:27 -07:00 committed by Aaron Durbin
parent 6228b9efb7
commit acfc149f7b
2 changed files with 3 additions and 0 deletions
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2
src/soc/intel/cannonlake/Kconfig
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@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC select UDELAY_TSC
select REG_SCRIPT select REG_SCRIPT
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select HAVE_HARD_RESET select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE select HAVE_INTEL_FIRMWARE
select INTEL_CAR_NEM_ENHANCED select INTEL_CAR_NEM_ENHANCED
@ -36,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO
select SUPPORT_CPU_UCODE_IN_CBFS
config UART_DEBUG config UART_DEBUG
bool "Enable UART debug port." bool "Enable UART debug port."

1
src/soc/intel/cannonlake/Makefile.inc
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@ -1,5 +1,6 @@
ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/tsc