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soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable 

As per TGL EDS doc:575681, two ways will be controlled with one bit
of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT
for TGL SoC.

Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-07-23 16:15:57 +05:30
parent baf922c798
commit ad08265740
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/tigerlake/Kconfig
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@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC select IOAPIC