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sb/intel/i82801ix: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB 

Use common code to detect ACPI S3.
Untested.

Change-Id: I618d4c25adb0d2b9bbd59a3b3b84beac78db1916
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2019-04-13 16:56:23 +02:00 committed by Patrick Rudolph
parent 41dad286d8
commit ad0b48222f
3 changed files with 3 additions and 16 deletions
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15
src/northbridge/intel/gm45/romstage.c
View File

@ -27,6 +27,7 @@
#include <northbridge/intel/gm45/gm45.h> #include <northbridge/intel/gm45/gm45.h>
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <string.h> #include <string.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@ -82,19 +83,7 @@ void mainboard_romstage_entry(unsigned long bist)
DMIBAR16(0x204) &= ~(3 << 10); DMIBAR16(0x204) &= ~(3 << 10);
/* Check for S3 resume. */ /* Check for S3 resume. */
const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); s3resume = southbridge_detect_s3_resume();
if (((pm1_cnt >> 10) & 7) == 5) {
if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
s3resume = 1;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
} else {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
}
}
/* RAM initialization */ /* RAM initialization */
enter_raminit_or_reset(); enter_raminit_or_reset();

1
src/southbridge/intel/i82801ix/Kconfig
View File

@ -26,6 +26,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
select HAVE_USBDEBUG_OPTIONS select HAVE_USBDEBUG_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES

3
src/southbridge/intel/i82801ix/lpc.c
View File

@ -283,9 +283,6 @@ static void i82801ix_power_options(struct device *dev)
will be constantly fired and OSPM must will be constantly fired and OSPM must
not know about it (ACPI spec says to not know about it (ACPI spec says to
ignore the bit). */ ignore the bit). */
reg32 = inl(pmbase + 0x04); // PM1_CNT
reg32 &= ~(7 << 10); // SLP_TYP
outl(reg32, pmbase + 0x04);
/* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */ /* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */
reg32 = inl(pmbase + 0x10); reg32 = inl(pmbase + 0x10);