GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

vendorcode/amd: Move 'static' to the beginning of declaration 

Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2019-06-22 09:52:12 +02:00 committed by Patrick Georgi
parent e29a6ac16a
commit ad1456f0d7
5 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/vendorcode/amd/cimx/sb800/AZALIA.c
View File

@ -61,7 +61,7 @@ VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN
* *
* *
*/ */
const static CODECENTRY AzaliaCodecAlc882Table[] = static const CODECENTRY AzaliaCodecAlc882Table[] =
{ {
{0x14, 0x01014010}, {0x14, 0x01014010},
{0x15, 0x01011012}, {0x15, 0x01011012},
@ -84,7 +84,7 @@ const static CODECENTRY AzaliaCodecAlc882Table[] =
* *
* *
*/ */
const static CODECENTRY AzaliaCodecAlc262Table[] = static const CODECENTRY AzaliaCodecAlc262Table[] =
{ {
{0x14, 0x01014010}, {0x14, 0x01014010},
{0x15, 0x411111F0}, {0x15, 0x411111F0},
@ -106,7 +106,7 @@ const static CODECENTRY AzaliaCodecAlc262Table[] =
* *
* *
*/ */
const static CODECENTRY AzaliaCodecAlc269Table[] = static const CODECENTRY AzaliaCodecAlc269Table[] =
{ {
{0x12, 0x99A30960}, {0x12, 0x99A30960},
{0x14, 0x99130110}, {0x14, 0x99130110},
@ -129,7 +129,7 @@ const static CODECENTRY AzaliaCodecAlc269Table[] =
* *
* *
*/ */
const static CODECENTRY AzaliaCodecAlc861Table[] = static const CODECENTRY AzaliaCodecAlc861Table[] =
{ {
{0x01, 0x8086C601}, {0x01, 0x8086C601},
{0x0B, 0x01014110}, {0x0B, 0x01014110},
@ -152,7 +152,7 @@ const static CODECENTRY AzaliaCodecAlc861Table[] =
* *
* *
*/ */
const static CODECENTRY AzaliaCodecAlc889Table[] = static const CODECENTRY AzaliaCodecAlc889Table[] =
{ {
{0x11, 0x411111F0}, {0x11, 0x411111F0},
{0x14, 0x01014010}, {0x14, 0x01014010},
@ -176,7 +176,7 @@ const static CODECENTRY AzaliaCodecAlc889Table[] =
* *
* *
*/ */
const static CODECENTRY AzaliaCodecAd1984Table[] = static const CODECENTRY AzaliaCodecAd1984Table[] =
{ {
{0x11, 0x0221401F}, {0x11, 0x0221401F},
{0x12, 0x90170110}, {0x12, 0x90170110},
@ -198,7 +198,7 @@ const static CODECENTRY AzaliaCodecAd1984Table[] =
* *
* *
*/ */
const static CODECENTRY FrontPanelAzaliaCodecTableList[] = static const CODECENTRY FrontPanelAzaliaCodecTableList[] =
{ {
{0x19, 0x02A19040}, {0x19, 0x02A19040},
{0x1b, 0x02214020}, {0x1b, 0x02214020},
@ -211,7 +211,7 @@ const static CODECENTRY FrontPanelAzaliaCodecTableList[] =
* *
* *
*/ */
const static CODECTBLLIST azaliaCodecTableList[] = static const CODECTBLLIST azaliaCodecTableList[] =
{ {
{0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
{0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},

6
src/vendorcode/amd/cimx/sb800/ECfanc.c
View File

@ -40,7 +40,7 @@
* *
* *
*/ */
const static UINT8 FunctionNumber[] = static const UINT8 FunctionNumber[] =
{ {
Fun_81, Fun_81,
Fun_83, Fun_83,
@ -55,7 +55,7 @@ const static UINT8 FunctionNumber[] =
* *
* *
*/ */
const static UINT8 MaxZone[] = static const UINT8 MaxZone[] =
{ {
4, 4,
4, 4,
@ -70,7 +70,7 @@ const static UINT8 MaxZone[] =
* *
* *
*/ */
const static UINT8 MaxRegister[] = static const UINT8 MaxRegister[] =
{ {
MSG_REG9, MSG_REG9,
MSG_REGB, MSG_REGB,

6
src/vendorcode/amd/cimx/sb800/SATA.c
View File

@ -176,7 +176,7 @@ shutdownUnconnectedSataPortClock (
* *
* *
*/ */
const static UINT32 sataIfCodeTable[] = static const UINT32 sataIfCodeTable[] =
{ {
0x01018F40, //sata class ID of IDE 0x01018F40, //sata class ID of IDE
0x01040040, //sata class ID of RAID 0x01040040, //sata class ID of RAID
@ -192,7 +192,7 @@ const static UINT32 sataIfCodeTable[] =
* *
* *
*/ */
const static UINT16 sataDeviceIDTable[] = static const UINT16 sataDeviceIDTable[] =
{ {
0x4390, //sata device ID of IDE 0x4390, //sata device ID of IDE
0x4392, //sata device ID of RAID 0x4392, //sata device ID of RAID
@ -208,7 +208,7 @@ const static UINT16 sataDeviceIDTable[] =
* *
* *
*/ */
const static SATAPHYSETTING sataPhyTable[] = static const SATAPHYSETTING sataPhyTable[] =
{ {
{0x3006, 0x0056A607}, {0x3006, 0x0056A607},
{0x2006, 0x00061400}, {0x2006, 0x00061400},

8
src/vendorcode/amd/cimx/sb800/SBCMN.c
View File

@ -83,7 +83,7 @@ VOID sbUsbPhySetting (IN UINT32 Value);
* sbEarlyPostByteInitTable - PCI device registers initial during early POST. * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
* *
*/ */
const static REG8MASK sbEarlyPostByteInitTable[] = static const REG8MASK sbEarlyPostByteInitTable[] =
{ {
// SMBUS Device (Bus 0, Dev 20, Func 0) // SMBUS Device (Bus 0, Dev 20, Func 0)
{0x00, SMBUS_BUS_DEV_FUN, 0}, {0x00, SMBUS_BUS_DEV_FUN, 0},
@ -134,7 +134,7 @@ const static REG8MASK sbEarlyPostByteInitTable[] =
* sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
* *
*/ */
const static AcpiRegWrite sbPmioEPostInitTable[] = static const AcpiRegWrite sbPmioEPostInitTable[] =
{ {
// HPET workaround // HPET workaround
{PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
@ -251,7 +251,7 @@ const static AcpiRegWrite sbPmioEPostInitTable[] =
* abTblEntry800 - AB-Link Configuration Table for SB800 * abTblEntry800 - AB-Link Configuration Table for SB800
* *
*/ */
const static ABTBLENTRY abTblEntry800[] = static const ABTBLENTRY abTblEntry800[] =
{ {
// RPR Enable downstream posted transactions to pass non-posted transactions. // RPR Enable downstream posted transactions to pass non-posted transactions.
{ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
@ -297,7 +297,7 @@ const static ABTBLENTRY abTblEntry800[] =
* SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
* *
*/ */
const static ABTBLENTRY SbPcieOrderRule[] = static const ABTBLENTRY SbPcieOrderRule[] =
{ {
// abPostPassNpDownStreamTbl // abPostPassNpDownStreamTbl
{ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},

4
src/vendorcode/amd/cimx/sb800/SBPort.c
View File

@ -49,7 +49,7 @@
/** /**
* sbPorInitPciTable - PCI device registers initial during the power on stage. * sbPorInitPciTable - PCI device registers initial during the power on stage.
*/ */
const static REG8MASK sbPorInitPciTable[] = static const REG8MASK sbPorInitPciTable[] =
{ {
// SATA device // SATA device
{0x00, SATA_BUS_DEV_FUN, 0}, {0x00, SATA_BUS_DEV_FUN, 0},
@ -82,7 +82,7 @@ const static REG8MASK sbPorInitPciTable[] =
/** /**
* sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
*/ */
const static AcpiRegWrite sbPmioPorInitTable[] = static const AcpiRegWrite sbPmioPorInitTable[] =
{ {
{PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},