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soc/intel/common: Limit BIOS region cache to 16MB 

Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake),
FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB
to save numbers of mtrr entries.

BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.

Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Lijian Zhao 2018-11-29 16:24:24 -08:00 committed by Duncan Laurie
parent 46f3fa825f
commit ad1e49afac
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/common/block/fast_spi/fast_spi.c
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@ -240,6 +240,12 @@ void fast_spi_cache_bios_region(void)
if (!bios_size)
return;
/* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will
* cause memory type conflict when setting memory type to write
* protection, so limit the cached bios region to be no more than 16MB.
* */
bios_size = MIN(bios_size, 16 * MiB);
/* Round to power of two */
alignment = 1UL << (log2_ceil(bios_size));
bios_size = ALIGN_UP(bios_size, alignment);