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soc/amd/picasso: Remove IOAPIC2 

Remove the Family 15h device.  It's not in Family 17h documentation
and isn't detectable with HDT.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ifa9c06f78f39a3ec3b555d4ecc542172cd44a0b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33990
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2019-06-22 16:15:06 -05:00 committed by Martin Roth
parent d881367c08
commit ad1fdac987
4 changed files with 2 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/amd/picasso/acpi.c
View File

@ -47,9 +47,6 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */

3
src/soc/amd/picasso/include/soc/iomap.h
View File

@ -18,8 +18,9 @@
#define __SOC_PICASSO_IOMAP_H__
/* MMIO Ranges */
/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */
#define SPI_BASE_ADDRESS 0xfec10000
#define IO_APIC2_ADDR 0xfec20000
#define ESPI_BASE_ADDRESS 0xfec20000
/*
* AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1].

26
src/soc/amd/picasso/include/soc/northbridge.h
View File

@ -20,28 +20,6 @@
#include <device/device.h>
#include <types.h>
/* D0F0 - Root Complex */
/* NB IOAPIC registers */
#define NB_IOAPIC_INDEX 0xf8
#define NB_IOAPIC_DATA 0xfc
#define NB_IOAPIC_FEATURE_CTRL 0x00
#define NB_IOAPIC_ADDRESS_LOW 0x01
#define NB_IOAPIC_ADDRESS_HIGH 0x02
#define NB_IOAPIC_GBIF_IRR 0x0f
#define NB_IOAPIC_BR0_IRR 0x10
#define NB_IOAPIC_BR1_IRR 0x11
#define NB_IOAPIC_BR2_IRR 0x12
#define NB_IOAPIC_BR3_IRR 0x13
#define NB_IOAPIC_BR4_IRR 0x14
#define NB_IOAPIC_APG_IRR 0x2f
#define NB_IOAPIC_SPG_IRR 0x30
#define NB_IOAPIC_SER_IRQ_IRR 0x31
#define NB_IOAPIC_SCRATCH0 0x3e
#define NB_IOAPIC_SCRATCH1 0x3f
#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0
/* D1F1 - HDA Configuration Registers */
#define HDA_DEV_CTRL_STATUS 0x60
#define HDA_NO_SNOOP_EN BIT(11)
@ -104,10 +82,6 @@ void amd_initcpuio(void);
void domain_enable_resources(struct device *dev);
void domain_set_resources(struct device *dev);
void fam15_finalize(void *chip_info);
uint32_t nb_ioapic_read(unsigned int index);
void nb_ioapic_write(unsigned int index, uint32_t value);
void *get_ap_entry_ptr(void);
void set_ap_entry_ptr(void *entry);
void set_warm_reset_flag(void);
int is_warm_reset(void);

18
src/soc/amd/picasso/northbridge.c
View File

@ -66,20 +66,12 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
static void read_resources(struct device *dev)
{
struct resource *res;
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
mmconf_resource(dev, MMIO_CONF_BASE);
/* NB IOAPIC2 resource */
res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */
res->base = IO_APIC2_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void set_resource(struct device *dev, struct resource *res, u32 nodeid)
@ -168,11 +160,6 @@ static void set_resources(struct device *dev)
assign_resources(bus);
}
static void northbridge_init(struct device *dev)
{
setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1);
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
@ -218,7 +205,6 @@ static struct device_operations northbridge_operations = {
.read_resources = read_resources,
.set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
.write_acpi_tables = agesa_write_acpi_tables,
.enable = 0,
@ -267,10 +253,6 @@ void fam15_finalize(void *chip_info)
{
u32 value;
/* TODO: move IOAPIC code to dsdt.asl */
pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0);
pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5);
/* disable No Snoop */
value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS);
value &= ~HDA_NO_SNOOP_EN;