intel/skylake: remove the gpio_fsp.h usage as skylake boards move gpio
config to coreboot completely BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I78e16e8079c4ee0c4fa70cb7a74ba039ee89398f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 6f1db1a2ffdbeb7dd21b4894f74d3feb44d69c49 Original-Change-Id: I8aafb0ef7d1b77cb8d386f4e73dc46ea3d8ee3a4 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294758 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11426 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
robbie zhang
Patrick Georgi
parent
c9d9729f5c
commit
ad3127f344
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@ -26,7 +26,6 @@
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#ifndef __ACPI__
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#include <stdint.h>
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#include <stddef.h>
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#include <soc/gpio_fsp.h>
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typedef uint32_t gpio_t;
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@ -1,512 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#ifndef _SOC_GPIO_FSP_H_
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#define _SOC_GPIO_FSP_H_
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#include <stdint.h>
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/*
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* GPP_Ax to GPP_Gx;
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* where x=24 [between GPIO Community A to F]
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* = 7 [only for GPIO Community G]
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*/
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#define MAX_GPIO_NUMBER 151 /* zero based */
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#define GPIO_LIST_END 0xffffffff
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/*
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* Skylake LP GPIO PIN to Pad Mapping
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*/
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#define GPIO_LP_GROUP_A 0x0
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#define GPIO_LP_GROUP_B 0x1
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#define GPIO_LP_GROUP_C 0x2
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#define GPIO_LP_GROUP_D 0x3
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#define GPIO_LP_GROUP_E 0x4
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#define GPIO_LP_GROUP_F 0x5
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#define GPIO_LP_GROUP_G 0x6
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#define GPIO_LP_GROUP_GPP_A 0x0200
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#define GPIO_LP_GROUP_GPP_B 0x0201
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#define GPIO_LP_GROUP_GPP_C 0x0202
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#define GPIO_LP_GROUP_GPP_D 0x0203
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#define GPIO_LP_GROUP_GPP_E 0x0204
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#define GPIO_LP_GROUP_GPP_F 0x0205
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#define GPIO_LP_GROUP_GPP_G 0x0206
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#define GPIO_GROUP_SHIFT 16
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#define MAX_GPIO_PIN_PER_GROUP 24
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/* GPIO TX STATE */
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#define B_PCH_GPIO_TX_STATE 0x0001
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#define N_PCH_GPIO_TX_STATE 0
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/* Interrupt number */
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#define B_PCH_GPIO_INTSEL 0x7F
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#define N_PCH_GPIO_INTSEL 0
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/* Structure for storing information about registers offset, community,
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* maximal pad number, smi status and smi enable for available groups
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*/
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typedef struct {
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u32 community;
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u32 padcfgoffset;
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u32 padpergroup;
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u32 smistsoffset;
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u32 smienoffset;
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} GPIO_GROUP_INFO;
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/*
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* GPIO Community 0 Registers are for GPP_A and GPP_B groups
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*/
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#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400
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#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0
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#define R_PCH_PCR_GPIO_GPP_A_SMI_STS 0x0180
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#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0184
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#define R_PCH_PCR_GPIO_GPP_A_SMI_EN 0x01A0
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#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x01A4
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/*
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* GPIO Community 1 Registers are for GPP_C, GPP_D, GPP_E groups
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*/
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#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400
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#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0
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#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580
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#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0180
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#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0184
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#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0188
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#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x01A0
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#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x01A4
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#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x01A8
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/*
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* GPIO Community 3 Registers are for GPP_F and GPP_G groups
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*/
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#define R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400
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#define R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0
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/*
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* GPIO Community 2 Registers are for GPP_DSW
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*/
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#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400
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#define READ 0
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#define WRITE 1
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/* If in GPIO_GROUP_INFO structure certain register doesn't exist
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* it will have value equal to NO_REGISTER_PROPERTY
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*/
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#define NO_REGISTER_PROPERTY (~0u)
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#define V_PCH_GPIO_GPP_A_PAD_MAX 24
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#define V_PCH_GPIO_GPP_B_PAD_MAX 24
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#define V_PCH_GPIO_GPP_C_PAD_MAX 24
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#define V_PCH_GPIO_GPP_D_PAD_MAX 24
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#define V_PCH_GPIO_GPP_E_PAD_MAX 24
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#define V_PCH_GPIO_GPP_F_PAD_MAX 24
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#define V_PCH_GPIO_GPP_G_PAD_MAX 8
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#define V_PCH_GPIO_GPD_PAD_MAX 12
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#define GPIO_GET_GROUP_INDEX(group) (group & 0xFF)
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#define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\
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GPIO_GET_GROUP_INDEX((pad >> 16)))
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#define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF)
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/* Number of pins used by SerialIo controllers */
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#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4
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#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2
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/* Below defines are based on GPIO_CONFIG structure fields */
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#define GPIO_CONF_PAD_MODE_MASK 0xF
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#define GPIO_CONF_PAD_MODE_BIT_POS 0
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/* GPIO Pad Mode */
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#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400)
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#define N_PCH_GPIO_PAD_MODE 10
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/* For any GpioPad usage in code use GPIO_PAD type*/
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typedef u32 GPIO_PAD;
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/* For any GpioGroup usage in code use GPIO_GROUP type */
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typedef u32 GPIO_GROUP;
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/*
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* GPIO configuration structure used for pin programming.
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* Structure contains fields that can be used to configure pad.
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*/
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typedef struct {
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/*
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Pad Mode
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Pad can be set as GPIO or one of its native functions.
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When in native mode setting Direction, OutputState, Interrupt is unnecessary.
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Refer to definition of GPIO_PAD_MODE.
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Refer to EDS for each native mode according to the pad.
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*/
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u32 PadMode : 4;
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/*
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Host Software Pad Ownership
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Set pad to ACPI mode or GPIO Driver Mode.
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Refer to definition of GPIO_HOSTSW_OWN.
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*/
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u32 HostSoftPadOwn : 2;
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/*
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GPIO Direction
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Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d
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isabling both.
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Refer to definition of GPIO_DIRECTION for supported settings.
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*/
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u32 Direction : 5;
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/*
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Output State
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Set Pad output value.
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Refer to definition of GPIO_OUTPUT_STATE for supported settings.
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This setting takes place when output is enabled.
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*/
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u32 OutputState : 2;
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/*
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GPIO Interrupt Configuration
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Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO
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A is in input mode.
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If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
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Refer to definition of GPIO_INT_CONFIG for supported settings.
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*/
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u32 InterruptConfig : 8;
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/*
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GPIO Power Configuration.
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This setting controls Pad Reset Configuration and Power Rail Type.
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Refer to definition of GPIO_RESET_CONFIG for supported settings.
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*/
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u32 PowerConfig : 4;
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/*
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GPIO Electrical Configuration
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This setting controls pads termination and voltage tolerance.
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Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
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*/
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u32 ElectricalConfig : 7;
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/*
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GPIO Lock Configuration
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This setting controls pads lock.
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Refer to definition of GPIO_LOCK_CONFIG for supported settings.
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*/
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u32 LockConfig : 3;
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/*
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Additional GPIO configuration
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Refer to definition of GPIO_OTHER_CONFIG for supported settings.
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*/
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u32 OtherSettings : 2;
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u32 RsvdBits : 27;
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} GPIO_CONFIG;
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typedef struct {
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GPIO_PAD GpioPad;
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GPIO_CONFIG GpioConfig;
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} GPIO_INIT_CONFIG;
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typedef enum {
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GpioHardwareDefault = 0x0
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} GPIO_HARDWARE_DEFAULT;
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/* GPIO Pad Mode */
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typedef enum {
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GpioPadModeGpio = 0x1,
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GpioPadModeNative1 = 0x3,
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GpioPadModeNative2 = 0x5,
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GpioPadModeNative3 = 0x7,
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GpioPadModeNative4 = 0x9,
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} GPIO_PAD_MODE;
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/* Host Software Pad Ownership modes */
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typedef enum {
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GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */
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GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */
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GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */
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} GPIO_HOSTSW_OWN;
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/* GPIO Direction */
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typedef enum {
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GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */
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GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */
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GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */
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GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */
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GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */
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GpioDirOut = 0x5, /* Set pad for output only */
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GpioDirNone = 0x7 /* Disable both output and input */
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} GPIO_DIRECTION;
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/* GPIO Output State */
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typedef enum {
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GpioOutDefault = 0x0,
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GpioOutLow = 0x1,
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GpioOutHigh = 0x3
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} GPIO_OUTPUT_STATE;
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/*
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* GPIO interrupt configuration
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* This setting is applicable only if GPIO is in input mode.
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* GPIO_INT_CONFIG allows to choose which interrupt is generted
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* (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level).
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* Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to
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* GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel
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* If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
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* Not all GPIO are capable of generating an SMI or NMI interrupt
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*/
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typedef enum {
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GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */
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GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */
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GpioIntNmi = 0x3, /* Enable NMI interrupt only */
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GpioIntSmi = 0x5, /* Enable SMI interrupt only */
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GpioIntSci = 0x9, /* Enable SCI interrupt only */
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GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */
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GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */
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GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */
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GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */
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GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */
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} GPIO_INT_CONFIG;
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/*
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* GPIO Power Configuration
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* GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified
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* Pad Register fields).
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*/
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typedef enum {
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GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */
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GpioResetPwrGood = 0x1, /* Powergood reset */
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GpioResetDeep = 0x3, /* Deep GPIO Reset */
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GpioResetNormal = 0x5, /* GPIO Reset */
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GpioResetResume = 0x7 /* Resume Reset */
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} GPIO_RESET_CONFIG;
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/*
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* GPIO Electrical Configuration
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* Set GPIO termination and Pad Tolerance (applicable only for some pads)
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* Field from GpioTermDefault to GpioTermNative can be OR'ed with
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* GpioTolerance1v8.
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*/
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typedef enum {
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GpioTermDefault = 0x0, /* Leave termination setting unmodified */
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GpioTermNone = 0x1, /* none */
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GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */
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GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */
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GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */
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GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */
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GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */
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GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */
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GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */
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GpioTermNative = 0x1F, /* Native function for pads termination */
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GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */
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GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */
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} GPIO_ELECTRICAL_CONFIG;
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/*
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* GPIO LockConfiguration
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* Set GPIO configuration lock and output state lock
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* GpioLockPadConfig and GpioLockOutputState can be OR'ed
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*/
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typedef enum {
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GpioLockDefault = 0x0, /* Leave lock setting unmodified */
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GpioPadConfigLock = 0x3, /* Lock Pad Configuration */
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GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */
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} GPIO_LOCK_CONFIG;
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/*
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* Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often
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* settings and for future extensions Supported settings:
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* - RX raw override to '1' - allows to override input value to '1'
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* This is applicable only if in input mode (both in GPIO and native usage)
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* The override takes place at the internal pad state directly from buffer
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* and before the RXINV.
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*/
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typedef enum {
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GpioRxRaw1Default = 0x0, /* Use default input override value */
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GpioRxRaw1Dis = 0x1, /* Don't override input */
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GpioRxRaw1En = 0x3 /* Override input to '1' */
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} GPIO_OTHER_CONFIG;
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/*
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* LP GPIO pins: Use below for functions from PCH GPIO Lib which
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* require GpioPad as argument. Encoding used here
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* has all information required by library functions
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*/
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#define GPIO_LP_GPP_A0 0x02000000
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#define GPIO_LP_GPP_A1 0x02000001
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#define GPIO_LP_GPP_A2 0x02000002
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#define GPIO_LP_GPP_A3 0x02000003
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#define GPIO_LP_GPP_A4 0x02000004
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#define GPIO_LP_GPP_A5 0x02000005
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#define GPIO_LP_GPP_A6 0x02000006
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#define GPIO_LP_GPP_A7 0x02000007
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#define GPIO_LP_GPP_A8 0x02000008
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#define GPIO_LP_GPP_A9 0x02000009
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#define GPIO_LP_GPP_A10 0x0200000A
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#define GPIO_LP_GPP_A11 0x0200000B
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#define GPIO_LP_GPP_A12 0x0200000C
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#define GPIO_LP_GPP_A13 0x0200000D
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#define GPIO_LP_GPP_A14 0x0200000E
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#define GPIO_LP_GPP_A15 0x0200000F
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#define GPIO_LP_GPP_A16 0x02000010
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#define GPIO_LP_GPP_A17 0x02000011
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#define GPIO_LP_GPP_A18 0x02000012
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#define GPIO_LP_GPP_A19 0x02000013
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#define GPIO_LP_GPP_A20 0x02000014
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#define GPIO_LP_GPP_A21 0x02000015
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#define GPIO_LP_GPP_A22 0x02000016
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#define GPIO_LP_GPP_A23 0x02000017
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#define GPIO_LP_GPP_B0 0x02010000
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#define GPIO_LP_GPP_B1 0x02010001
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#define GPIO_LP_GPP_B2 0x02010002
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#define GPIO_LP_GPP_B3 0x02010003
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#define GPIO_LP_GPP_B4 0x02010004
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#define GPIO_LP_GPP_B5 0x02010005
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#define GPIO_LP_GPP_B6 0x02010006
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#define GPIO_LP_GPP_B7 0x02010007
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#define GPIO_LP_GPP_B8 0x02010008
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#define GPIO_LP_GPP_B9 0x02010009
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#define GPIO_LP_GPP_B10 0x0201000A
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#define GPIO_LP_GPP_B11 0x0201000B
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#define GPIO_LP_GPP_B12 0x0201000C
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#define GPIO_LP_GPP_B13 0x0201000D
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#define GPIO_LP_GPP_B14 0x0201000E
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#define GPIO_LP_GPP_B15 0x0201000F
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#define GPIO_LP_GPP_B16 0x02010010
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#define GPIO_LP_GPP_B17 0x02010011
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#define GPIO_LP_GPP_B18 0x02010012
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||||
#define GPIO_LP_GPP_B19 0x02010013
|
||||
#define GPIO_LP_GPP_B20 0x02010014
|
||||
#define GPIO_LP_GPP_B21 0x02010015
|
||||
#define GPIO_LP_GPP_B22 0x02010016
|
||||
#define GPIO_LP_GPP_B23 0x02010017
|
||||
#define GPIO_LP_GPP_C0 0x02020000
|
||||
#define GPIO_LP_GPP_C1 0x02020001
|
||||
#define GPIO_LP_GPP_C2 0x02020002
|
||||
#define GPIO_LP_GPP_C3 0x02020003
|
||||
#define GPIO_LP_GPP_C4 0x02020004
|
||||
#define GPIO_LP_GPP_C5 0x02020005
|
||||
#define GPIO_LP_GPP_C6 0x02020006
|
||||
#define GPIO_LP_GPP_C7 0x02020007
|
||||
#define GPIO_LP_GPP_C8 0x02020008
|
||||
#define GPIO_LP_GPP_C9 0x02020009
|
||||
#define GPIO_LP_GPP_C10 0x0202000A
|
||||
#define GPIO_LP_GPP_C11 0x0202000B
|
||||
#define GPIO_LP_GPP_C12 0x0202000C
|
||||
#define GPIO_LP_GPP_C13 0x0202000D
|
||||
#define GPIO_LP_GPP_C14 0x0202000E
|
||||
#define GPIO_LP_GPP_C15 0x0202000F
|
||||
#define GPIO_LP_GPP_C16 0x02020010
|
||||
#define GPIO_LP_GPP_C17 0x02020011
|
||||
#define GPIO_LP_GPP_C18 0x02020012
|
||||
#define GPIO_LP_GPP_C19 0x02020013
|
||||
#define GPIO_LP_GPP_C20 0x02020014
|
||||
#define GPIO_LP_GPP_C21 0x02020015
|
||||
#define GPIO_LP_GPP_C22 0x02020016
|
||||
#define GPIO_LP_GPP_C23 0x02020017
|
||||
#define GPIO_LP_GPP_D0 0x02030000
|
||||
#define GPIO_LP_GPP_D1 0x02030001
|
||||
#define GPIO_LP_GPP_D2 0x02030002
|
||||
#define GPIO_LP_GPP_D3 0x02030003
|
||||
#define GPIO_LP_GPP_D4 0x02030004
|
||||
#define GPIO_LP_GPP_D5 0x02030005
|
||||
#define GPIO_LP_GPP_D6 0x02030006
|
||||
#define GPIO_LP_GPP_D7 0x02030007
|
||||
#define GPIO_LP_GPP_D8 0x02030008
|
||||
#define GPIO_LP_GPP_D9 0x02030009
|
||||
#define GPIO_LP_GPP_D10 0x0203000A
|
||||
#define GPIO_LP_GPP_D11 0x0203000B
|
||||
#define GPIO_LP_GPP_D12 0x0203000C
|
||||
#define GPIO_LP_GPP_D13 0x0203000D
|
||||
#define GPIO_LP_GPP_D14 0x0203000E
|
||||
#define GPIO_LP_GPP_D15 0x0203000F
|
||||
#define GPIO_LP_GPP_D16 0x02030010
|
||||
#define GPIO_LP_GPP_D17 0x02030011
|
||||
#define GPIO_LP_GPP_D18 0x02030012
|
||||
#define GPIO_LP_GPP_D19 0x02030013
|
||||
#define GPIO_LP_GPP_D20 0x02030014
|
||||
#define GPIO_LP_GPP_D21 0x02030015
|
||||
#define GPIO_LP_GPP_D22 0x02030016
|
||||
#define GPIO_LP_GPP_D23 0x02030017
|
||||
#define GPIO_LP_GPP_E0 0x02040000
|
||||
#define GPIO_LP_GPP_E1 0x02040001
|
||||
#define GPIO_LP_GPP_E2 0x02040002
|
||||
#define GPIO_LP_GPP_E3 0x02040003
|
||||
#define GPIO_LP_GPP_E4 0x02040004
|
||||
#define GPIO_LP_GPP_E5 0x02040005
|
||||
#define GPIO_LP_GPP_E6 0x02040006
|
||||
#define GPIO_LP_GPP_E7 0x02040007
|
||||
#define GPIO_LP_GPP_E8 0x02040008
|
||||
#define GPIO_LP_GPP_E9 0x02040009
|
||||
#define GPIO_LP_GPP_E10 0x0204000A
|
||||
#define GPIO_LP_GPP_E11 0x0204000B
|
||||
#define GPIO_LP_GPP_E12 0x0204000C
|
||||
#define GPIO_LP_GPP_E13 0x0204000D
|
||||
#define GPIO_LP_GPP_E14 0x0204000E
|
||||
#define GPIO_LP_GPP_E15 0x0204000F
|
||||
#define GPIO_LP_GPP_E16 0x02040010
|
||||
#define GPIO_LP_GPP_E17 0x02040011
|
||||
#define GPIO_LP_GPP_E18 0x02040012
|
||||
#define GPIO_LP_GPP_E19 0x02040013
|
||||
#define GPIO_LP_GPP_E20 0x02040014
|
||||
#define GPIO_LP_GPP_E21 0x02040015
|
||||
#define GPIO_LP_GPP_E22 0x02040016
|
||||
#define GPIO_LP_GPP_E23 0x02040017
|
||||
#define GPIO_LP_GPP_F0 0x02050000
|
||||
#define GPIO_LP_GPP_F1 0x02050001
|
||||
#define GPIO_LP_GPP_F2 0x02050002
|
||||
#define GPIO_LP_GPP_F3 0x02050003
|
||||
#define GPIO_LP_GPP_F4 0x02050004
|
||||
#define GPIO_LP_GPP_F5 0x02050005
|
||||
#define GPIO_LP_GPP_F6 0x02050006
|
||||
#define GPIO_LP_GPP_F7 0x02050007
|
||||
#define GPIO_LP_GPP_F8 0x02050008
|
||||
#define GPIO_LP_GPP_F9 0x02050009
|
||||
#define GPIO_LP_GPP_F10 0x0205000A
|
||||
#define GPIO_LP_GPP_F11 0x0205000B
|
||||
#define GPIO_LP_GPP_F12 0x0205000C
|
||||
#define GPIO_LP_GPP_F13 0x0205000D
|
||||
#define GPIO_LP_GPP_F14 0x0205000E
|
||||
#define GPIO_LP_GPP_F15 0x0205000F
|
||||
#define GPIO_LP_GPP_F16 0x02050010
|
||||
#define GPIO_LP_GPP_F17 0x02050011
|
||||
#define GPIO_LP_GPP_F18 0x02050012
|
||||
#define GPIO_LP_GPP_F19 0x02050013
|
||||
#define GPIO_LP_GPP_F20 0x02050014
|
||||
#define GPIO_LP_GPP_F21 0x02050015
|
||||
#define GPIO_LP_GPP_F22 0x02050016
|
||||
#define GPIO_LP_GPP_F23 0x02050017
|
||||
#define GPIO_LP_GPP_G0 0x02060000
|
||||
#define GPIO_LP_GPP_G1 0x02060001
|
||||
#define GPIO_LP_GPP_G2 0x02060002
|
||||
#define GPIO_LP_GPP_G3 0x02060003
|
||||
#define GPIO_LP_GPP_G4 0x02060004
|
||||
#define GPIO_LP_GPP_G5 0x02060005
|
||||
#define GPIO_LP_GPP_G6 0x02060006
|
||||
#define GPIO_LP_GPP_G7 0x02060007
|
||||
#define GPIO_LP_GPD0 0x02070000
|
||||
#define GPIO_LP_GPD1 0x02070001
|
||||
#define GPIO_LP_GPD2 0x02070002
|
||||
#define GPIO_LP_GPD3 0x02070003
|
||||
#define GPIO_LP_GPD4 0x02070004
|
||||
#define GPIO_LP_GPD5 0x02070005
|
||||
#define GPIO_LP_GPD6 0x02070006
|
||||
#define GPIO_LP_GPD7 0x02070007
|
||||
#define GPIO_LP_GPD8 0x02070008
|
||||
#define GPIO_LP_GPD9 0x02070009
|
||||
#define GPIO_LP_GPD10 0x0207000A
|
||||
#define GPIO_LP_GPD11 0x0207000B
|
||||
|
||||
#define END_OF_GPIO_TABLE 0xFFFFFFFF
|
||||
#endif
|
||||
Loading…
Reference in New Issue