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google/sarien: Increase BIOS region to 28MB 

Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.

BUG=b:119267832
TEST=Build and boot fine on sarien platform.

Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Lijian Zhao 2018-11-29 16:46:49 -08:00 committed by Patrick Georgi
parent 378ec8b0de
commit ad41f55123
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/google/sarien/chromeos.fmd
View File

@ -1,11 +1,11 @@
FLASH@0xfe000000 0x2000000 {
SI_ALL@0x0 0x1000000 {
SI_ALL@0x0 0x400000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x100000
SI_GBE@0x101000 0x2000
SI_ME@0x103000 0xefd000
SI_ME@0x103000 0x2fd000
}
SI_BIOS@0x1000000 0x1000000 {
SI_BIOS@0x400000 0x1c00000 {
RW_SECTION_A@0x0 0x280000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x26ffc0
@ -30,8 +30,8 @@ FLASH@0xfe000000 0x2000000 {
RW_NVRAM@0x2a000 0x6000
}
CONSOLE@0x530000 0x20000
RW_LEGACY(CBFS)@0x550000 0x6b0000
WP_RO@0xc00000 0x400000 {
RW_LEGACY(CBFS)@0x550000 0x12b0000
WP_RO@0x1800000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x3f0000 {