From ad42d9c22baa0ad5abbdb29a7c159b76220404d3 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 19 Apr 2023 18:30:53 +0530 Subject: [PATCH] =?UTF-8?q?soc/intel/meteorlake:=C2=A0Send=20CSE=20EOP=20A?= =?UTF-8?q?sync=20CMD=20early?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample which causes idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/rex sku to ChromeOS and observed ~100ms of boot time savings (across warm and cold reset scenarios) Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/74561 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Tarun Tuli --- src/soc/intel/meteorlake/chip.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 60f85ba983..1f7eab81ea 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -151,6 +152,22 @@ void soc_init_pre_device(void *chip_info) /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pcie_rp_table()); + + /* + * Earlier when coreboot used to send EOP at late as possible caused + * issue of delayed response from CSE since CSE was busy loading payload. + * To resolve the issue, EOP should be sent earlier than current sequence + * in the boot sequence at BS_DEV_INIT. + * + * Intel CSE team recommends to send EOP close to FW init (between FSP-S + * exit and current boot sequence) to reduce message response time from + * CSE hence moving sending EOP to earlier stage. + */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) { + printk(BIOS_INFO, "Sending EOP early from SoC\n"); + cse_send_end_of_post(); + } } static void cpu_fill_ssdt(const struct device *dev)