diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c
index 0be93aa571..e676fb1ec4 100644
--- a/src/soc/amd/stoneyridge/tsc_freq.c
+++ b/src/soc/amd/stoneyridge/tsc_freq.c
@@ -1,17 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <amdblocks/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/tsc.h>
 #include <console/console.h>
 #include <soc/pci_devs.h>
+#include <soc/msr.h>
 #include <device/pci_ops.h>
 
 unsigned long tsc_freq_mhz(void)
 {
-	msr_t msr;
-	uint8_t cpufid;
-	uint8_t cpudid;
+	union pstate_msr pstate_reg;
 	uint8_t boost_states;
 
 	/*
@@ -23,12 +23,9 @@ unsigned long tsc_freq_mhz(void)
 	boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
 			>> 2) & 0x7;
 
-	msr = rdmsr(PSTATE_MSR(boost_states));
-	if (!(msr.hi & 0x80000000))
+	pstate_reg.raw = rdmsr(PSTATE_MSR(boost_states)).raw;
+	if (!pstate_reg.pstate_en)
 		die("Unknown error: cannot determine P-state 0\n");
 
-	cpufid = (msr.lo & 0x3f);
-	cpudid = (msr.lo & 0x1c0) >> 6;
-
-	return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+	return get_pstate_core_freq(pstate_reg);
 }