timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
parent
e96ade6981
commit
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@ -12,7 +12,7 @@ __weak void platform_romstage_postram(void) { /* no-op */ }
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void main(void)
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void main(void)
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{
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{
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timestamp_add_now(TS_START_ROMSTAGE);
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timestamp_add_now(TS_ROMSTAGE_START);
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console_init();
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console_init();
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exception_init();
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exception_init();
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@ -30,7 +30,7 @@ void main(void)
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if (!cbmem_online())
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if (!cbmem_online())
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cbmem_initialize();
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cbmem_initialize();
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timestamp_add_now(TS_START_POSTCAR);
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timestamp_add_now(TS_POSTCAR_START);
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display_mtrrs();
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display_mtrrs();
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@ -192,7 +192,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
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load_postcar_cbfs(&prog, pcf);
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load_postcar_cbfs(&prog, pcf);
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/* As postcar exist, it's end of romstage here */
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/* As postcar exist, it's end of romstage here */
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timestamp_add_now(TS_END_ROMSTAGE);
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timestamp_add_now(TS_ROMSTAGE_END);
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console_time_report();
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console_time_report();
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@ -19,23 +19,23 @@ struct timestamp_table {
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} __packed;
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} __packed;
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enum timestamp_id {
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enum timestamp_id {
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TS_START_ROMSTAGE = 1,
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TS_ROMSTAGE_START = 1,
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TS_BEFORE_INITRAM = 2,
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TS_INITRAM_START = 2,
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TS_AFTER_INITRAM = 3,
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TS_INITRAM_END = 3,
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TS_END_ROMSTAGE = 4,
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TS_ROMSTAGE_END = 4,
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TS_START_VBOOT = 5,
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TS_VBOOT_START = 5,
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TS_END_VBOOT = 6,
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TS_VBOOT_END = 6,
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TS_START_COPYRAM = 8,
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TS_COPYRAM_START = 8,
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TS_END_COPYRAM = 9,
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TS_COPYRAM_END = 9,
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TS_START_RAMSTAGE = 10,
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TS_RAMSTAGE_START = 10,
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TS_START_BOOTBLOCK = 11,
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TS_BOOTBLOCK_START = 11,
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TS_END_BOOTBLOCK = 12,
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TS_BOOTBLOCK_END = 12,
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TS_START_COPYROM = 13,
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TS_COPYROM_START = 13,
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TS_END_COPYROM = 14,
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TS_COPYROM_END = 14,
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TS_START_ULZMA = 15,
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TS_ULZMA_START = 15,
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TS_END_ULZMA = 16,
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TS_ULZMA_END = 16,
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TS_START_ULZ4F = 17,
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TS_ULZ4F_START = 17,
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TS_END_ULZ4F = 18,
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TS_ULZ4F_END = 18,
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TS_DEVICE_ENUMERATE = 30,
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TS_DEVICE_ENUMERATE = 30,
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TS_DEVICE_CONFIGURE = 40,
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TS_DEVICE_CONFIGURE = 40,
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TS_DEVICE_ENABLE = 50,
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TS_DEVICE_ENABLE = 50,
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@ -50,8 +50,8 @@ enum timestamp_id {
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TS_LOAD_PAYLOAD = 90,
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TS_LOAD_PAYLOAD = 90,
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TS_ACPI_WAKE_JUMP = 98,
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TS_ACPI_WAKE_JUMP = 98,
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TS_SELFBOOT_JUMP = 99,
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TS_SELFBOOT_JUMP = 99,
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TS_START_POSTCAR = 100,
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TS_POSTCAR_START = 100,
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TS_END_POSTCAR = 101,
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TS_POSTCAR_END = 101,
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TS_DELAY_START = 110,
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TS_DELAY_START = 110,
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TS_DELAY_END = 111,
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TS_DELAY_END = 111,
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TS_READ_UCODE_START = 112,
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TS_READ_UCODE_START = 112,
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@ -60,67 +60,67 @@ enum timestamp_id {
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TS_ELOG_INIT_END = 115,
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TS_ELOG_INIT_END = 115,
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/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
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/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
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TS_START_COPYVER = 501,
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TS_COPYVER_START = 501,
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TS_END_COPYVER = 502,
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TS_COPYVER_END = 502,
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TS_START_TPMINIT = 503,
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TS_TPMINIT_START = 503,
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TS_END_TPMINIT = 504,
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TS_TPMINIT_END = 504,
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TS_START_VERIFY_SLOT = 505,
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TS_VERIFY_SLOT_START = 505,
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TS_END_VERIFY_SLOT = 506,
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TS_VERIFY_SLOT_END = 506,
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TS_START_HASH_BODY = 507,
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TS_HASH_BODY_START = 507,
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TS_DONE_LOADING = 508,
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TS_LOADING_END = 508,
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TS_DONE_HASHING = 509,
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TS_HASHING_END = 509,
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TS_END_HASH_BODY = 510,
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TS_HASH_BODY_END = 510,
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TS_START_TPMPCR = 511,
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TS_TPMPCR_START = 511,
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TS_END_TPMPCR = 512,
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TS_TPMPCR_END = 512,
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TS_START_TPMLOCK = 513,
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TS_TPMLOCK_START = 513,
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TS_END_TPMLOCK = 514,
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TS_TPMLOCK_END = 514,
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TS_START_EC_SYNC = 515,
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TS_EC_SYNC_START = 515,
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TS_EC_HASH_READY = 516,
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TS_EC_HASH_READY = 516,
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TS_EC_POWER_LIMIT_WAIT = 517,
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TS_EC_POWER_LIMIT_WAIT = 517,
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TS_END_EC_SYNC = 518,
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TS_EC_SYNC_END = 518,
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TS_START_COPYVPD = 550,
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TS_COPYVPD_START = 550,
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TS_END_COPYVPD_RO = 551,
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TS_COPYVPD_RO_END = 551,
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TS_END_COPYVPD_RW = 552,
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TS_COPYVPD_RW_END = 552,
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TS_START_TPM_ENABLE_UPDATE = 553,
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TS_TPM_ENABLE_UPDATE_START = 553,
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TS_END_TPM_ENABLE_UPDATE = 554,
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TS_TPM_ENABLE_UPDATE_END = 554,
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/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
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/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
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TS_AGESA_INIT_RESET_START = 900,
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TS_AGESA_INIT_RESET_START = 900,
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TS_AGESA_INIT_RESET_DONE = 901,
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TS_AGESA_INIT_RESET_END = 901,
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TS_AGESA_INIT_EARLY_START = 902,
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TS_AGESA_INIT_EARLY_START = 902,
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TS_AGESA_INIT_EARLY_DONE = 903,
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TS_AGESA_INIT_EARLY_END = 903,
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TS_AGESA_INIT_POST_START = 904,
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TS_AGESA_INIT_POST_START = 904,
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TS_AGESA_INIT_POST_DONE = 905,
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TS_AGESA_INIT_POST_END = 905,
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TS_AGESA_INIT_ENV_START = 906,
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TS_AGESA_INIT_ENV_START = 906,
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TS_AGESA_INIT_ENV_DONE = 907,
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TS_AGESA_INIT_ENV_END = 907,
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TS_AGESA_INIT_MID_START = 908,
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TS_AGESA_INIT_MID_START = 908,
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TS_AGESA_INIT_MID_DONE = 909,
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TS_AGESA_INIT_MID_END = 909,
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TS_AGESA_INIT_LATE_START = 910,
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TS_AGESA_INIT_LATE_START = 910,
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TS_AGESA_INIT_LATE_DONE = 911,
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TS_AGESA_INIT_LATE_END = 911,
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TS_AGESA_INIT_RTB_START = 912,
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TS_AGESA_INIT_RTB_START = 912,
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TS_AGESA_INIT_RTB_DONE = 913,
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TS_AGESA_INIT_RTB_END = 913,
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TS_AGESA_INIT_RESUME_START = 914,
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TS_AGESA_INIT_RESUME_START = 914,
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TS_AGESA_INIT_RESUME_DONE = 915,
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TS_AGESA_INIT_RESUME_END = 915,
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TS_AGESA_S3_LATE_START = 916,
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TS_AGESA_S3_LATE_START = 916,
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TS_AGESA_S3_LATE_DONE = 917,
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TS_AGESA_S3_LATE_END = 917,
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TS_AGESA_S3_FINAL_START = 918,
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TS_AGESA_S3_FINAL_START = 918,
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TS_AGESA_S3_FINAL_DONE = 919,
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TS_AGESA_S3_FINAL_END = 919,
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TS_AMD_APOB_READ_START = 920,
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TS_AMD_APOB_READ_START = 920,
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TS_AMD_APOB_ERASE_START = 921,
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TS_AMD_APOB_ERASE_START = 921,
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TS_AMD_APOB_WRITE_START = 922,
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TS_AMD_APOB_WRITE_START = 922,
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TS_AMD_APOB_DONE = 923,
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TS_AMD_APOB_END = 923,
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/* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
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/* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
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TS_ME_INFORM_DRAM_WAIT = 940,
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TS_ME_INFORM_DRAM_START = 940,
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TS_ME_INFORM_DRAM_DONE = 941,
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TS_ME_INFORM_DRAM_END = 941,
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TS_ME_BEFORE_END_OF_POST = 942,
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TS_ME_END_OF_POST_START = 942,
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TS_ME_AFTER_END_OF_POST = 943,
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TS_ME_END_OF_POST_END = 943,
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TS_ME_BOOT_STALL_DONE = 944,
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TS_ME_BOOT_STALL_END = 944,
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TS_ME_ICC_CONFIG_START = 945,
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TS_ME_ICC_CONFIG_START = 945,
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TS_ME_HOST_BOOT_PREP_DONE = 946,
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TS_ME_HOST_BOOT_PREP_END = 946,
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TS_ME_RECEIVED_CRDA_FROM_PMC = 947,
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TS_ME_RECEIVED_CRDA_FROM_PMC = 947,
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TS_START_CSE_FW_SYNC = 948,
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TS_CSE_FW_SYNC_START = 948,
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TS_END_CSE_FW_SYNC = 949,
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TS_CSE_FW_SYNC_END = 949,
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/* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */
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/* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */
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TS_FSP_MEMORY_INIT_START = 950,
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TS_FSP_MEMORY_INIT_START = 950,
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@ -129,12 +129,12 @@ enum timestamp_id {
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TS_FSP_TEMP_RAM_EXIT_END = 953,
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TS_FSP_TEMP_RAM_EXIT_END = 953,
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TS_FSP_SILICON_INIT_START = 954,
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TS_FSP_SILICON_INIT_START = 954,
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TS_FSP_SILICON_INIT_END = 955,
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TS_FSP_SILICON_INIT_END = 955,
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TS_FSP_BEFORE_ENUMERATE = 956,
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TS_FSP_ENUMERATE_START = 956,
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TS_FSP_AFTER_ENUMERATE = 957,
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TS_FSP_ENUMERATE_END = 957,
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TS_FSP_BEFORE_FINALIZE = 958,
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TS_FSP_FINALIZE_START = 958,
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TS_FSP_AFTER_FINALIZE = 959,
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TS_FSP_FINALIZE_END = 959,
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TS_FSP_BEFORE_END_OF_FIRMWARE = 960,
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TS_FSP_END_OF_FIRMWARE_START = 960,
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TS_FSP_AFTER_END_OF_FIRMWARE = 961,
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TS_FSP_END_OF_FIRMWARE_END = 961,
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TS_FSP_MULTI_PHASE_SI_INIT_START = 962,
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TS_FSP_MULTI_PHASE_SI_INIT_START = 962,
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TS_FSP_MULTI_PHASE_SI_INIT_END = 963,
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TS_FSP_MULTI_PHASE_SI_INIT_END = 963,
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TS_FSP_MEMORY_INIT_LOAD = 970,
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TS_FSP_MEMORY_INIT_LOAD = 970,
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@ -161,7 +161,7 @@ enum timestamp_id {
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TS_VB_READ_KERNEL_DONE = 1050,
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TS_VB_READ_KERNEL_DONE = 1050,
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TS_VB_VBOOT_DONE = 1100,
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TS_VB_VBOOT_DONE = 1100,
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TS_START_KERNEL = 1101,
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TS_KERNEL_START = 1101,
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TS_KERNEL_DECOMPRESSION = 1102,
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TS_KERNEL_DECOMPRESSION = 1102,
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};
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};
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@ -171,23 +171,23 @@ static const struct timestamp_id_to_name {
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} timestamp_ids[] = {
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} timestamp_ids[] = {
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/* Marker to report base_time. */
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/* Marker to report base_time. */
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{ 0, "1st timestamp" },
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{ 0, "1st timestamp" },
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{ TS_START_ROMSTAGE, "start of romstage" },
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{ TS_ROMSTAGE_START, "start of romstage" },
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{ TS_BEFORE_INITRAM, "before RAM initialization" },
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{ TS_INITRAM_START, "before RAM initialization" },
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{ TS_AFTER_INITRAM, "after RAM initialization" },
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{ TS_INITRAM_END, "after RAM initialization" },
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{ TS_END_ROMSTAGE, "end of romstage" },
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{ TS_ROMSTAGE_END, "end of romstage" },
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{ TS_START_VBOOT, "start of verified boot" },
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{ TS_VBOOT_START, "start of verified boot" },
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{ TS_END_VBOOT, "end of verified boot" },
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{ TS_VBOOT_END, "end of verified boot" },
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{ TS_START_COPYRAM, "starting to load ramstage" },
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{ TS_COPYRAM_START, "starting to load ramstage" },
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{ TS_END_COPYRAM, "finished loading ramstage" },
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{ TS_COPYRAM_END, "finished loading ramstage" },
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{ TS_START_RAMSTAGE, "start of ramstage" },
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{ TS_RAMSTAGE_START, "start of ramstage" },
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{ TS_START_BOOTBLOCK, "start of bootblock" },
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{ TS_BOOTBLOCK_START, "start of bootblock" },
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{ TS_END_BOOTBLOCK, "end of bootblock" },
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{ TS_BOOTBLOCK_END, "end of bootblock" },
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{ TS_START_COPYROM, "starting to load romstage" },
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{ TS_COPYROM_START, "starting to load romstage" },
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{ TS_END_COPYROM, "finished loading romstage" },
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{ TS_COPYROM_END, "finished loading romstage" },
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{ TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" },
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{ TS_ULZMA_START, "starting LZMA decompress (ignore for x86)" },
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{ TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" },
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{ TS_ULZMA_END, "finished LZMA decompress (ignore for x86)" },
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{ TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" },
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{ TS_ULZ4F_START, "starting LZ4 decompress (ignore for x86)" },
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{ TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" },
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{ TS_ULZ4F_END, "finished LZ4 decompress (ignore for x86)" },
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{ TS_DEVICE_ENUMERATE, "device enumeration" },
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{ TS_DEVICE_ENUMERATE, "device enumeration" },
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{ TS_DEVICE_CONFIGURE, "device configuration" },
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{ TS_DEVICE_CONFIGURE, "device configuration" },
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{ TS_DEVICE_ENABLE, "device enable" },
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{ TS_DEVICE_ENABLE, "device enable" },
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@ -209,31 +209,31 @@ static const struct timestamp_id_to_name {
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{ TS_ELOG_INIT_START, "started elog init" },
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{ TS_ELOG_INIT_START, "started elog init" },
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{ TS_ELOG_INIT_END, "finished elog init" },
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{ TS_ELOG_INIT_END, "finished elog init" },
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{ TS_START_COPYVER, "starting to load verstage" },
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{ TS_COPYVER_START, "starting to load verstage" },
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{ TS_END_COPYVER, "finished loading verstage" },
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{ TS_COPYVER_END, "finished loading verstage" },
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{ TS_START_TPMINIT, "starting to initialize TPM" },
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{ TS_TPMINIT_START, "starting to initialize TPM" },
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{ TS_END_TPMINIT, "finished TPM initialization" },
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{ TS_TPMINIT_END, "finished TPM initialization" },
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{ TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" },
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{ TS_VERIFY_SLOT_START, "starting to verify keyblock/preamble (RSA)" },
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{ TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" },
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{ TS_VERIFY_SLOT_END, "finished verifying keyblock/preamble (RSA)" },
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{ TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " },
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{ TS_HASH_BODY_START, "starting to verify body (load+SHA2+RSA) " },
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{ TS_DONE_LOADING, "finished loading body" },
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{ TS_LOADING_END, "finished loading body" },
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{ TS_DONE_HASHING, "finished calculating body hash (SHA2)" },
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{ TS_HASHING_END, "finished calculating body hash (SHA2)" },
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{ TS_END_HASH_BODY, "finished verifying body signature (RSA)" },
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{ TS_HASH_BODY_END, "finished verifying body signature (RSA)" },
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{ TS_START_TPMPCR, "starting TPM PCR extend" },
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{ TS_TPMPCR_START, "starting TPM PCR extend" },
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{ TS_END_TPMPCR, "finished TPM PCR extend" },
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{ TS_TPMPCR_END, "finished TPM PCR extend" },
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{ TS_START_TPMLOCK, "starting locking TPM" },
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{ TS_TPMLOCK_START, "starting locking TPM" },
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{ TS_END_TPMLOCK, "finished locking TPM" },
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{ TS_TPMLOCK_END, "finished locking TPM" },
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{ TS_START_TPM_ENABLE_UPDATE, "started TPM enable update" },
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{ TS_TPM_ENABLE_UPDATE_START, "started TPM enable update" },
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{ TS_END_TPM_ENABLE_UPDATE, "finished TPM enable update" },
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{ TS_TPM_ENABLE_UPDATE_END, "finished TPM enable update" },
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{ TS_START_COPYVPD, "starting to load Chrome OS VPD" },
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{ TS_COPYVPD_START, "starting to load Chrome OS VPD" },
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{ TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" },
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{ TS_COPYVPD_RO_END, "finished loading Chrome OS VPD (RO)" },
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{ TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" },
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{ TS_COPYVPD_RW_END, "finished loading Chrome OS VPD (RW)" },
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{ TS_START_EC_SYNC, "starting EC software sync" },
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{ TS_EC_SYNC_START, "starting EC software sync" },
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{ TS_EC_HASH_READY, "EC vboot hash ready" },
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{ TS_EC_HASH_READY, "EC vboot hash ready" },
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{ TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" },
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{ TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" },
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{ TS_END_EC_SYNC, "finished EC software sync" },
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{ TS_EC_SYNC_END, "finished EC software sync" },
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{ TS_DC_START, "depthcharge start" },
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{ TS_DC_START, "depthcharge start" },
|
||||||
{ TS_RO_PARAMS_INIT, "RO parameter init" },
|
{ TS_RO_PARAMS_INIT, "RO parameter init" },
|
||||||
|
@ -247,45 +247,45 @@ static const struct timestamp_id_to_name {
|
||||||
{ TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" },
|
{ TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" },
|
||||||
{ TS_VB_VBOOT_DONE, "finished vboot kernel verification" },
|
{ TS_VB_VBOOT_DONE, "finished vboot kernel verification" },
|
||||||
{ TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" },
|
{ TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" },
|
||||||
{ TS_START_KERNEL, "jumping to kernel" },
|
{ TS_KERNEL_START, "jumping to kernel" },
|
||||||
|
|
||||||
/* AMD related timestamps */
|
/* AMD related timestamps */
|
||||||
{ TS_AGESA_INIT_RESET_START, "calling AmdInitReset" },
|
{ TS_AGESA_INIT_RESET_START, "calling AmdInitReset" },
|
||||||
{ TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" },
|
{ TS_AGESA_INIT_RESET_END, "back from AmdInitReset" },
|
||||||
{ TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" },
|
{ TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" },
|
||||||
{ TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" },
|
{ TS_AGESA_INIT_EARLY_END, "back from AmdInitEarly" },
|
||||||
{ TS_AGESA_INIT_POST_START, "calling AmdInitPost" },
|
{ TS_AGESA_INIT_POST_START, "calling AmdInitPost" },
|
||||||
{ TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" },
|
{ TS_AGESA_INIT_POST_END, "back from AmdInitPost" },
|
||||||
{ TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" },
|
{ TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" },
|
||||||
{ TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" },
|
{ TS_AGESA_INIT_ENV_END, "back from AmdInitEnv" },
|
||||||
{ TS_AGESA_INIT_MID_START, "calling AmdInitMid" },
|
{ TS_AGESA_INIT_MID_START, "calling AmdInitMid" },
|
||||||
{ TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" },
|
{ TS_AGESA_INIT_MID_END, "back from AmdInitMid" },
|
||||||
{ TS_AGESA_INIT_LATE_START, "calling AmdInitLate" },
|
{ TS_AGESA_INIT_LATE_START, "calling AmdInitLate" },
|
||||||
{ TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" },
|
{ TS_AGESA_INIT_LATE_END, "back from AmdInitLate" },
|
||||||
{ TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" },
|
{ TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" },
|
||||||
{ TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" },
|
{ TS_AGESA_INIT_RTB_END, "back from AmdInitRtb/AmdS3Save" },
|
||||||
{ TS_AGESA_INIT_RESUME_START, "calling AmdInitResume" },
|
{ TS_AGESA_INIT_RESUME_START, "calling AmdInitResume" },
|
||||||
{ TS_AGESA_INIT_RESUME_DONE, "back from AmdInitResume" },
|
{ TS_AGESA_INIT_RESUME_END, "back from AmdInitResume" },
|
||||||
{ TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore" },
|
{ TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore" },
|
||||||
{ TS_AGESA_S3_LATE_DONE, "back from AmdS3LateRestore" },
|
{ TS_AGESA_S3_LATE_END, "back from AmdS3LateRestore" },
|
||||||
{ TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" },
|
{ TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" },
|
||||||
{ TS_AGESA_S3_FINAL_DONE, "back from AmdS3FinalRestore" },
|
{ TS_AGESA_S3_FINAL_END, "back from AmdS3FinalRestore" },
|
||||||
{ TS_AMD_APOB_READ_START, "starting APOB read" },
|
{ TS_AMD_APOB_READ_START, "starting APOB read" },
|
||||||
{ TS_AMD_APOB_ERASE_START, "starting APOB erase" },
|
{ TS_AMD_APOB_ERASE_START, "starting APOB erase" },
|
||||||
{ TS_AMD_APOB_WRITE_START, "starting APOB write" },
|
{ TS_AMD_APOB_WRITE_START, "starting APOB write" },
|
||||||
{ TS_AMD_APOB_DONE, "finished APOB" },
|
{ TS_AMD_APOB_END, "finished APOB" },
|
||||||
|
|
||||||
/* Intel ME related timestamps */
|
/* Intel ME related timestamps */
|
||||||
{ TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"},
|
{ TS_ME_INFORM_DRAM_START, "waiting for ME acknowledgement of raminit"},
|
||||||
{ TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"},
|
{ TS_ME_INFORM_DRAM_END, "finished waiting for ME response"},
|
||||||
{ TS_ME_BEFORE_END_OF_POST, "before sending EOP to ME"},
|
{ TS_ME_END_OF_POST_START, "before sending EOP to ME"},
|
||||||
{ TS_ME_AFTER_END_OF_POST, "after sending EOP to ME"},
|
{ TS_ME_END_OF_POST_END, "after sending EOP to ME"},
|
||||||
{ TS_ME_BOOT_STALL_DONE, "CSE sent 'Boot Stall Done' to PMC"},
|
{ TS_ME_BOOT_STALL_END, "CSE sent 'Boot Stall Done' to PMC"},
|
||||||
{ TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"},
|
{ TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"},
|
||||||
{ TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"},
|
{ TS_ME_HOST_BOOT_PREP_END, "CSE sent 'Host BIOS Prep Done' to PMC"},
|
||||||
{ TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"},
|
{ TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"},
|
||||||
{ TS_START_CSE_FW_SYNC, "starting CSE firmware sync"},
|
{ TS_CSE_FW_SYNC_START, "starting CSE firmware sync"},
|
||||||
{ TS_END_CSE_FW_SYNC, "finished CSE firmware sync"},
|
{ TS_CSE_FW_SYNC_END, "finished CSE firmware sync"},
|
||||||
{ TS_ME_ROM_START, "CSME ROM started execution"},
|
{ TS_ME_ROM_START, "CSME ROM started execution"},
|
||||||
|
|
||||||
/* FSP related timestamps */
|
/* FSP related timestamps */
|
||||||
|
@ -297,20 +297,20 @@ static const struct timestamp_id_to_name {
|
||||||
{ TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" },
|
{ TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" },
|
||||||
{ TS_FSP_MULTI_PHASE_SI_INIT_START, "calling FspMultiPhaseSiInit" },
|
{ TS_FSP_MULTI_PHASE_SI_INIT_START, "calling FspMultiPhaseSiInit" },
|
||||||
{ TS_FSP_MULTI_PHASE_SI_INIT_END, "returning from FspMultiPhaseSiInit" },
|
{ TS_FSP_MULTI_PHASE_SI_INIT_END, "returning from FspMultiPhaseSiInit" },
|
||||||
{ TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" },
|
{ TS_FSP_ENUMERATE_START, "calling FspNotify(AfterPciEnumeration)" },
|
||||||
{ TS_FSP_AFTER_ENUMERATE,
|
{ TS_FSP_ENUMERATE_END,
|
||||||
"returning from FspNotify(AfterPciEnumeration)" },
|
"returning from FspNotify(AfterPciEnumeration)" },
|
||||||
{ TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" },
|
{ TS_FSP_FINALIZE_START, "calling FspNotify(ReadyToBoot)" },
|
||||||
{ TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" },
|
{ TS_FSP_FINALIZE_END, "returning from FspNotify(ReadyToBoot)" },
|
||||||
{ TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" },
|
{ TS_FSP_END_OF_FIRMWARE_START, "calling FspNotify(EndOfFirmware)" },
|
||||||
{ TS_FSP_AFTER_END_OF_FIRMWARE,
|
{ TS_FSP_END_OF_FIRMWARE_END,
|
||||||
"returning from FspNotify(EndOfFirmware)" },
|
"returning from FspNotify(EndOfFirmware)" },
|
||||||
|
|
||||||
{ TS_FSP_MEMORY_INIT_LOAD, "loading FSP-M" },
|
{ TS_FSP_MEMORY_INIT_LOAD, "loading FSP-M" },
|
||||||
{ TS_FSP_SILICON_INIT_LOAD, "loading FSP-S" },
|
{ TS_FSP_SILICON_INIT_LOAD, "loading FSP-S" },
|
||||||
|
|
||||||
{ TS_START_POSTCAR, "start of postcar" },
|
{ TS_POSTCAR_START, "start of postcar" },
|
||||||
{ TS_END_POSTCAR, "end of postcar" },
|
{ TS_POSTCAR_END, "end of postcar" },
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -60,7 +60,7 @@ static void romstage_main(void)
|
||||||
|
|
||||||
asmlinkage void car_stage_entry(void)
|
asmlinkage void car_stage_entry(void)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
/* Assumes the hardware was set up during the bootblock */
|
/* Assumes the hardware was set up during the bootblock */
|
||||||
console_init();
|
console_init();
|
||||||
|
|
|
@ -28,69 +28,69 @@ static const struct agesa_mapping entrypoint[] = {
|
||||||
.func = AMD_INIT_RESET,
|
.func = AMD_INIT_RESET,
|
||||||
.name = "AmdInitReset",
|
.name = "AmdInitReset",
|
||||||
.entry_id = TS_AGESA_INIT_RESET_START,
|
.entry_id = TS_AGESA_INIT_RESET_START,
|
||||||
.exit_id = TS_AGESA_INIT_RESET_DONE,
|
.exit_id = TS_AGESA_INIT_RESET_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_INIT_EARLY,
|
.func = AMD_INIT_EARLY,
|
||||||
.name = "AmdInitEarly",
|
.name = "AmdInitEarly",
|
||||||
.entry_id = TS_AGESA_INIT_EARLY_START,
|
.entry_id = TS_AGESA_INIT_EARLY_START,
|
||||||
.exit_id = TS_AGESA_INIT_EARLY_DONE,
|
.exit_id = TS_AGESA_INIT_EARLY_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_INIT_POST,
|
.func = AMD_INIT_POST,
|
||||||
.name = "AmdInitPost",
|
.name = "AmdInitPost",
|
||||||
.entry_id = TS_AGESA_INIT_POST_START,
|
.entry_id = TS_AGESA_INIT_POST_START,
|
||||||
.exit_id = TS_AGESA_INIT_POST_DONE,
|
.exit_id = TS_AGESA_INIT_POST_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_INIT_RESUME,
|
.func = AMD_INIT_RESUME,
|
||||||
.name = "AmdInitResume",
|
.name = "AmdInitResume",
|
||||||
.entry_id = TS_AGESA_INIT_RESUME_START,
|
.entry_id = TS_AGESA_INIT_RESUME_START,
|
||||||
.exit_id = TS_AGESA_INIT_RESUME_DONE,
|
.exit_id = TS_AGESA_INIT_RESUME_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_INIT_ENV,
|
.func = AMD_INIT_ENV,
|
||||||
.name = "AmdInitEnv",
|
.name = "AmdInitEnv",
|
||||||
.entry_id = TS_AGESA_INIT_ENV_START,
|
.entry_id = TS_AGESA_INIT_ENV_START,
|
||||||
.exit_id = TS_AGESA_INIT_ENV_DONE,
|
.exit_id = TS_AGESA_INIT_ENV_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_INIT_MID,
|
.func = AMD_INIT_MID,
|
||||||
.name = "AmdInitMid",
|
.name = "AmdInitMid",
|
||||||
.entry_id = TS_AGESA_INIT_MID_START,
|
.entry_id = TS_AGESA_INIT_MID_START,
|
||||||
.exit_id = TS_AGESA_INIT_MID_DONE,
|
.exit_id = TS_AGESA_INIT_MID_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_INIT_LATE,
|
.func = AMD_INIT_LATE,
|
||||||
.name = "AmdInitLate",
|
.name = "AmdInitLate",
|
||||||
.entry_id = TS_AGESA_INIT_LATE_START,
|
.entry_id = TS_AGESA_INIT_LATE_START,
|
||||||
.exit_id = TS_AGESA_INIT_LATE_DONE,
|
.exit_id = TS_AGESA_INIT_LATE_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_S3LATE_RESTORE,
|
.func = AMD_S3LATE_RESTORE,
|
||||||
.name = "AmdS3LateRestore",
|
.name = "AmdS3LateRestore",
|
||||||
.entry_id = TS_AGESA_S3_LATE_START,
|
.entry_id = TS_AGESA_S3_LATE_START,
|
||||||
.exit_id = TS_AGESA_S3_LATE_DONE,
|
.exit_id = TS_AGESA_S3_LATE_END,
|
||||||
},
|
},
|
||||||
#if !defined(AMD_S3_SAVE_REMOVED)
|
#if !defined(AMD_S3_SAVE_REMOVED)
|
||||||
{
|
{
|
||||||
.func = AMD_S3_SAVE,
|
.func = AMD_S3_SAVE,
|
||||||
.name = "AmdS3Save",
|
.name = "AmdS3Save",
|
||||||
.entry_id = TS_AGESA_INIT_RTB_START,
|
.entry_id = TS_AGESA_INIT_RTB_START,
|
||||||
.exit_id = TS_AGESA_INIT_RTB_DONE,
|
.exit_id = TS_AGESA_INIT_RTB_END,
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
.func = AMD_S3FINAL_RESTORE,
|
.func = AMD_S3FINAL_RESTORE,
|
||||||
.name = "AmdS3FinalRestore",
|
.name = "AmdS3FinalRestore",
|
||||||
.entry_id = TS_AGESA_S3_FINAL_START,
|
.entry_id = TS_AGESA_S3_FINAL_START,
|
||||||
.exit_id = TS_AGESA_S3_FINAL_DONE,
|
.exit_id = TS_AGESA_S3_FINAL_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.func = AMD_INIT_RTB,
|
.func = AMD_INIT_RTB,
|
||||||
.name = "AmdInitRtb",
|
.name = "AmdInitRtb",
|
||||||
.entry_id = TS_AGESA_INIT_RTB_START,
|
.entry_id = TS_AGESA_INIT_RTB_START,
|
||||||
.exit_id = TS_AGESA_INIT_RTB_DONE,
|
.exit_id = TS_AGESA_INIT_RTB_END,
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -40,7 +40,7 @@ static void romstage_main(void)
|
||||||
|
|
||||||
fill_sysinfo(cb);
|
fill_sysinfo(cb);
|
||||||
|
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
board_BeforeAgesa(cb);
|
board_BeforeAgesa(cb);
|
||||||
|
|
||||||
|
@ -55,14 +55,14 @@ static void romstage_main(void)
|
||||||
|
|
||||||
agesa_execute_state(cb, AMD_INIT_EARLY);
|
agesa_execute_state(cb, AMD_INIT_EARLY);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
if (!cb->s3resume)
|
if (!cb->s3resume)
|
||||||
agesa_execute_state(cb, AMD_INIT_POST);
|
agesa_execute_state(cb, AMD_INIT_POST);
|
||||||
else
|
else
|
||||||
agesa_execute_state(cb, AMD_INIT_RESUME);
|
agesa_execute_state(cb, AMD_INIT_RESUME);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
/* Work around AGESA setting all memory as WB on normal
|
/* Work around AGESA setting all memory as WB on normal
|
||||||
* boot path.
|
* boot path.
|
||||||
|
|
|
@ -134,17 +134,17 @@ void fsp_notify(u32 phase)
|
||||||
notify_phase_params.Phase = phase;
|
notify_phase_params.Phase = phase;
|
||||||
|
|
||||||
if (phase == EnumInitPhaseReadyToBoot) {
|
if (phase == EnumInitPhaseReadyToBoot) {
|
||||||
timestamp_add_now(TS_FSP_BEFORE_FINALIZE);
|
timestamp_add_now(TS_FSP_FINALIZE_START);
|
||||||
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
|
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
|
||||||
} else {
|
} else {
|
||||||
timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
|
timestamp_add_now(TS_FSP_ENUMERATE_START);
|
||||||
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
|
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
|
||||||
}
|
}
|
||||||
|
|
||||||
status = notify_phase_proc(¬ify_phase_params);
|
status = notify_phase_proc(¬ify_phase_params);
|
||||||
|
|
||||||
timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
|
timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
|
||||||
TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
|
TS_FSP_FINALIZE_END : TS_FSP_ENUMERATE_END);
|
||||||
|
|
||||||
if (status != 0)
|
if (status != 0)
|
||||||
printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n",
|
printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n",
|
||||||
|
|
|
@ -26,7 +26,7 @@ static void raminit_common(struct romstage_params *params)
|
||||||
|
|
||||||
post_code(0x32);
|
post_code(0x32);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
s3wake = params->power_state->prev_sleep_state == ACPI_S3;
|
s3wake = params->power_state->prev_sleep_state == ACPI_S3;
|
||||||
|
|
||||||
|
@ -66,7 +66,7 @@ static void raminit_common(struct romstage_params *params)
|
||||||
|
|
||||||
/* Initialize RAM */
|
/* Initialize RAM */
|
||||||
raminit(params);
|
raminit(params);
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
/* Save MRC output */
|
/* Save MRC output */
|
||||||
if (CONFIG(CACHE_MRC_SETTINGS)) {
|
if (CONFIG(CACHE_MRC_SETTINGS)) {
|
||||||
|
@ -100,7 +100,7 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
|
||||||
|
|
||||||
post_code(0x30);
|
post_code(0x30);
|
||||||
|
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
/* Display parameters */
|
/* Display parameters */
|
||||||
if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
|
if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
|
||||||
|
|
|
@ -380,9 +380,9 @@ void fsp_memory_init(bool s3wake)
|
||||||
die("FSPM XIP base does not match: %p vs %p\n",
|
die("FSPM XIP base does not match: %p vs %p\n",
|
||||||
(void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog));
|
(void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog));
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
do_fsp_memory_init(&context, s3wake);
|
do_fsp_memory_init(&context, s3wake);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
}
|
}
|
||||||
|
|
|
@ -23,24 +23,24 @@ static const struct fsp_notify_phase_data notify_data[] = {
|
||||||
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
|
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
|
||||||
.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
|
.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
|
||||||
.post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE,
|
.post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE,
|
||||||
.timestamp_before = TS_FSP_BEFORE_ENUMERATE,
|
.timestamp_before = TS_FSP_ENUMERATE_START,
|
||||||
.timestamp_after = TS_FSP_AFTER_ENUMERATE,
|
.timestamp_after = TS_FSP_ENUMERATE_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.notify_phase = READY_TO_BOOT,
|
.notify_phase = READY_TO_BOOT,
|
||||||
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
|
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
|
||||||
.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
|
.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
|
||||||
.post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE,
|
.post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE,
|
||||||
.timestamp_before = TS_FSP_BEFORE_FINALIZE,
|
.timestamp_before = TS_FSP_FINALIZE_START,
|
||||||
.timestamp_after = TS_FSP_AFTER_FINALIZE,
|
.timestamp_after = TS_FSP_FINALIZE_END,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.notify_phase = END_OF_FIRMWARE,
|
.notify_phase = END_OF_FIRMWARE,
|
||||||
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
|
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
|
||||||
.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
|
.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
|
||||||
.post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
|
.post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
|
||||||
.timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE,
|
.timestamp_before = TS_FSP_END_OF_FIRMWARE_START,
|
||||||
.timestamp_after = TS_FSP_AFTER_END_OF_FIRMWARE,
|
.timestamp_after = TS_FSP_END_OF_FIRMWARE_END,
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -126,7 +126,7 @@ static void cbmem_add_cros_vpd(int is_recovery)
|
||||||
{
|
{
|
||||||
struct vpd_cbmem *cbmem;
|
struct vpd_cbmem *cbmem;
|
||||||
|
|
||||||
timestamp_add_now(TS_START_COPYVPD);
|
timestamp_add_now(TS_COPYVPD_START);
|
||||||
|
|
||||||
init_vpd_rdevs();
|
init_vpd_rdevs();
|
||||||
|
|
||||||
|
@ -154,7 +154,7 @@ static void cbmem_add_cros_vpd(int is_recovery)
|
||||||
printk(BIOS_ERR, "Couldn't read RO VPD\n");
|
printk(BIOS_ERR, "Couldn't read RO VPD\n");
|
||||||
cbmem->ro_size = ro_size = 0;
|
cbmem->ro_size = ro_size = 0;
|
||||||
}
|
}
|
||||||
timestamp_add_now(TS_END_COPYVPD_RO);
|
timestamp_add_now(TS_COPYVPD_RO_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (rw_size) {
|
if (rw_size) {
|
||||||
|
@ -163,7 +163,7 @@ static void cbmem_add_cros_vpd(int is_recovery)
|
||||||
printk(BIOS_ERR, "Couldn't read RW VPD\n");
|
printk(BIOS_ERR, "Couldn't read RW VPD\n");
|
||||||
cbmem->rw_size = rw_size = 0;
|
cbmem->rw_size = rw_size = 0;
|
||||||
}
|
}
|
||||||
timestamp_add_now(TS_END_COPYVPD_RW);
|
timestamp_add_now(TS_COPYVPD_RW_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
init_vpd_rdevs_from_cbmem();
|
init_vpd_rdevs_from_cbmem();
|
||||||
|
|
|
@ -39,7 +39,7 @@ void bootblock_main_with_timestamp(uint64_t base_timestamp,
|
||||||
timestamps[i].entry_stamp);
|
timestamps[i].entry_stamp);
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add_now(TS_START_BOOTBLOCK);
|
timestamp_add_now(TS_BOOTBLOCK_START);
|
||||||
|
|
||||||
bootblock_soc_early_init();
|
bootblock_soc_early_init();
|
||||||
bootblock_mainboard_early_init();
|
bootblock_mainboard_early_init();
|
||||||
|
@ -63,7 +63,7 @@ void bootblock_main_with_timestamp(uint64_t base_timestamp,
|
||||||
tpm_setup(s3resume);
|
tpm_setup(s3resume);
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add_now(TS_END_BOOTBLOCK);
|
timestamp_add_now(TS_BOOTBLOCK_END);
|
||||||
|
|
||||||
run_romstage();
|
run_romstage();
|
||||||
}
|
}
|
||||||
|
|
|
@ -215,9 +215,9 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) {
|
if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) {
|
||||||
timestamp_add_now(TS_START_ULZ4F);
|
timestamp_add_now(TS_ULZ4F_START);
|
||||||
out_size = ulz4fn(map, in_size, buffer, buffer_size);
|
out_size = ulz4fn(map, in_size, buffer, buffer_size);
|
||||||
timestamp_add_now(TS_END_ULZ4F);
|
timestamp_add_now(TS_ULZ4F_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
rdev_munmap(rdev, map);
|
rdev_munmap(rdev, map);
|
||||||
|
@ -233,9 +233,9 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b
|
||||||
|
|
||||||
if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) {
|
if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) {
|
||||||
/* Note: timestamp not useful for memory-mapped media (x86) */
|
/* Note: timestamp not useful for memory-mapped media (x86) */
|
||||||
timestamp_add_now(TS_START_ULZMA);
|
timestamp_add_now(TS_ULZMA_START);
|
||||||
out_size = ulzman(map, in_size, buffer, buffer_size);
|
out_size = ulzman(map, in_size, buffer, buffer_size);
|
||||||
timestamp_add_now(TS_END_ULZMA);
|
timestamp_add_now(TS_ULZMA_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
rdev_munmap(rdev, map);
|
rdev_munmap(rdev, map);
|
||||||
|
|
|
@ -23,8 +23,8 @@ struct bootblock_arg arg = {
|
||||||
.base_timestamp = 0,
|
.base_timestamp = 0,
|
||||||
.num_timestamps = 2,
|
.num_timestamps = 2,
|
||||||
.timestamps = {
|
.timestamps = {
|
||||||
{ .entry_id = TS_START_ULZ4F },
|
{ .entry_id = TS_ULZ4F_START },
|
||||||
{ .entry_id = TS_END_ULZ4F },
|
{ .entry_id = TS_ULZ4F_END },
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -62,14 +62,14 @@ static bool extract(struct region *region, struct fit_image_node *node)
|
||||||
true_size = node->size;
|
true_size = node->size;
|
||||||
break;
|
break;
|
||||||
case CBFS_COMPRESS_LZMA:
|
case CBFS_COMPRESS_LZMA:
|
||||||
timestamp_add_now(TS_START_ULZMA);
|
timestamp_add_now(TS_ULZMA_START);
|
||||||
true_size = ulzman(node->data, node->size, dst, region->size);
|
true_size = ulzman(node->data, node->size, dst, region->size);
|
||||||
timestamp_add_now(TS_END_ULZMA);
|
timestamp_add_now(TS_ULZMA_END);
|
||||||
break;
|
break;
|
||||||
case CBFS_COMPRESS_LZ4:
|
case CBFS_COMPRESS_LZ4:
|
||||||
timestamp_add_now(TS_START_ULZ4F);
|
timestamp_add_now(TS_ULZ4F_START);
|
||||||
true_size = ulz4fn(node->data, node->size, dst, region->size);
|
true_size = ulz4fn(node->data, node->size, dst, region->size);
|
||||||
timestamp_add_now(TS_END_ULZ4F);
|
timestamp_add_now(TS_ULZ4F_END);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return true;
|
return true;
|
||||||
|
@ -240,5 +240,5 @@ void fit_payload(struct prog *payload, void *data)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add_now(TS_START_KERNEL);
|
timestamp_add_now(TS_KERNEL_START);
|
||||||
}
|
}
|
||||||
|
|
|
@ -457,7 +457,7 @@ void main(void)
|
||||||
*/
|
*/
|
||||||
cbmem_initialize();
|
cbmem_initialize();
|
||||||
|
|
||||||
timestamp_add_now(TS_START_RAMSTAGE);
|
timestamp_add_now(TS_RAMSTAGE_START);
|
||||||
post_code(POST_ENTRY_HARDWAREMAIN);
|
post_code(POST_ENTRY_HARDWAREMAIN);
|
||||||
|
|
||||||
/* Handoff sleep type from romstage. */
|
/* Handoff sleep type from romstage. */
|
||||||
|
|
|
@ -24,7 +24,7 @@ void run_romstage(void)
|
||||||
|
|
||||||
vboot_run_logic();
|
vboot_run_logic();
|
||||||
|
|
||||||
timestamp_add_now(TS_START_COPYROM);
|
timestamp_add_now(TS_COPYROM_START);
|
||||||
|
|
||||||
if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) {
|
if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) {
|
||||||
if (legacy_romstage_select_and_load(&romstage))
|
if (legacy_romstage_select_and_load(&romstage))
|
||||||
|
@ -34,7 +34,7 @@ void run_romstage(void)
|
||||||
goto fail;
|
goto fail;
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add_now(TS_END_COPYROM);
|
timestamp_add_now(TS_COPYROM_END);
|
||||||
|
|
||||||
console_time_report();
|
console_time_report();
|
||||||
|
|
||||||
|
@ -90,11 +90,11 @@ void run_ramstage(void)
|
||||||
PROG_INIT(PROG_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
|
PROG_INIT(PROG_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
|
||||||
|
|
||||||
if (ENV_POSTCAR)
|
if (ENV_POSTCAR)
|
||||||
timestamp_add_now(TS_END_POSTCAR);
|
timestamp_add_now(TS_POSTCAR_END);
|
||||||
|
|
||||||
/* Call "end of romstage" here if postcar stage doesn't exist */
|
/* Call "end of romstage" here if postcar stage doesn't exist */
|
||||||
if (ENV_ROMSTAGE)
|
if (ENV_ROMSTAGE)
|
||||||
timestamp_add_now(TS_END_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_END);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Only x86 systems using ramstage stage cache currently take the same
|
* Only x86 systems using ramstage stage cache currently take the same
|
||||||
|
@ -105,7 +105,7 @@ void run_ramstage(void)
|
||||||
|
|
||||||
vboot_run_logic();
|
vboot_run_logic();
|
||||||
|
|
||||||
timestamp_add_now(TS_START_COPYRAM);
|
timestamp_add_now(TS_COPYRAM_START);
|
||||||
|
|
||||||
if (ENV_X86) {
|
if (ENV_X86) {
|
||||||
if (load_relocatable_ramstage(&ramstage))
|
if (load_relocatable_ramstage(&ramstage))
|
||||||
|
@ -117,7 +117,7 @@ void run_ramstage(void)
|
||||||
|
|
||||||
stage_cache_add(STAGE_RAMSTAGE, &ramstage);
|
stage_cache_add(STAGE_RAMSTAGE, &ramstage);
|
||||||
|
|
||||||
timestamp_add_now(TS_END_COPYRAM);
|
timestamp_add_now(TS_COPYRAM_END);
|
||||||
|
|
||||||
console_time_report();
|
console_time_report();
|
||||||
|
|
||||||
|
|
|
@ -72,18 +72,18 @@ static int load_one_segment(uint8_t *dest,
|
||||||
switch (compression) {
|
switch (compression) {
|
||||||
case CBFS_COMPRESS_LZMA: {
|
case CBFS_COMPRESS_LZMA: {
|
||||||
printk(BIOS_DEBUG, "using LZMA\n");
|
printk(BIOS_DEBUG, "using LZMA\n");
|
||||||
timestamp_add_now(TS_START_ULZMA);
|
timestamp_add_now(TS_ULZMA_START);
|
||||||
len = ulzman(src, len, dest, memsz);
|
len = ulzman(src, len, dest, memsz);
|
||||||
timestamp_add_now(TS_END_ULZMA);
|
timestamp_add_now(TS_ULZMA_END);
|
||||||
if (!len) /* Decompression Error. */
|
if (!len) /* Decompression Error. */
|
||||||
return 0;
|
return 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case CBFS_COMPRESS_LZ4: {
|
case CBFS_COMPRESS_LZ4: {
|
||||||
printk(BIOS_DEBUG, "using LZ4\n");
|
printk(BIOS_DEBUG, "using LZ4\n");
|
||||||
timestamp_add_now(TS_START_ULZ4F);
|
timestamp_add_now(TS_ULZ4F_START);
|
||||||
len = ulz4fn(src, len, dest, memsz);
|
len = ulz4fn(src, len, dest, memsz);
|
||||||
timestamp_add_now(TS_END_ULZ4F);
|
timestamp_add_now(TS_ULZ4F_END);
|
||||||
if (!len) /* Decompression Error. */
|
if (!len) /* Decompression Error. */
|
||||||
return 0;
|
return 0;
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -123,7 +123,7 @@ void main(void)
|
||||||
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
|
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
|
||||||
|
|
||||||
timestamp_init(timestamp_get());
|
timestamp_init(timestamp_get());
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
/* Clock must be initialized before console_init, otherwise you may need
|
/* Clock must be initialized before console_init, otherwise you may need
|
||||||
* to re-initialize serial console drivers again. */
|
* to re-initialize serial console drivers again. */
|
||||||
|
@ -134,11 +134,11 @@ void main(void)
|
||||||
|
|
||||||
setup_power(is_resume);
|
setup_power(is_resume);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
setup_memory(mem, is_resume);
|
setup_memory(mem, is_resume);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
/* This needs to happen on normal boots and on resume. */
|
/* This needs to happen on normal boots and on resume. */
|
||||||
trustzone_init();
|
trustzone_init();
|
||||||
|
|
|
@ -24,7 +24,7 @@
|
||||||
static void __attribute__((noinline)) romstage(void)
|
static void __attribute__((noinline)) romstage(void)
|
||||||
{
|
{
|
||||||
timestamp_init(0);
|
timestamp_init(0);
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
console_init();
|
console_init();
|
||||||
exception_init();
|
exception_init();
|
||||||
|
|
|
@ -24,7 +24,7 @@
|
||||||
static void __attribute__((noinline)) romstage(void)
|
static void __attribute__((noinline)) romstage(void)
|
||||||
{
|
{
|
||||||
timestamp_init(0);
|
timestamp_init(0);
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
console_init();
|
console_init();
|
||||||
exception_init();
|
exception_init();
|
||||||
|
|
|
@ -25,7 +25,7 @@
|
||||||
static void __attribute__((noinline)) romstage(void)
|
static void __attribute__((noinline)) romstage(void)
|
||||||
{
|
{
|
||||||
timestamp_init(0);
|
timestamp_init(0);
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
console_init();
|
console_init();
|
||||||
exception_init();
|
exception_init();
|
||||||
|
|
|
@ -212,7 +212,7 @@ void main(void)
|
||||||
power_init_failed = setup_power(is_resume);
|
power_init_failed = setup_power(is_resume);
|
||||||
|
|
||||||
timestamp_init(timestamp_get());
|
timestamp_init(timestamp_get());
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
/* Clock must be initialized before console_init, otherwise you may need
|
/* Clock must be initialized before console_init, otherwise you may need
|
||||||
* to re-initialize serial console drivers again. */
|
* to re-initialize serial console drivers again. */
|
||||||
|
@ -228,11 +228,11 @@ void main(void)
|
||||||
/* re-initialize PMIC I2C channel after (re-)setting system clocks */
|
/* re-initialize PMIC I2C channel after (re-)setting system clocks */
|
||||||
i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
|
i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
setup_memory(&mem_timings, is_resume);
|
setup_memory(&mem_timings, is_resume);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
primitive_mem_test();
|
primitive_mem_test();
|
||||||
|
|
||||||
|
|
|
@ -64,7 +64,7 @@ static void sdmmc_power_off(void)
|
||||||
|
|
||||||
void main(void)
|
void main(void)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
console_init();
|
console_init();
|
||||||
exception_init();
|
exception_init();
|
||||||
|
@ -77,11 +77,11 @@ void main(void)
|
||||||
/* vdd_log 1200mv is enough for ddr run 666Mhz */
|
/* vdd_log 1200mv is enough for ddr run 666Mhz */
|
||||||
regulate_vdd_log(1200);
|
regulate_vdd_log(1200);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
sdram_init(get_sdram_config());
|
sdram_init(get_sdram_config());
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
|
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
|
||||||
mmu_config_range((uintptr_t)_dram/MiB,
|
mmu_config_range((uintptr_t)_dram/MiB,
|
||||||
|
|
|
@ -58,7 +58,7 @@ static void configure_l2ctlr(void)
|
||||||
|
|
||||||
void main(void)
|
void main(void)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
console_init();
|
console_init();
|
||||||
exception_init();
|
exception_init();
|
||||||
|
@ -68,11 +68,11 @@ void main(void)
|
||||||
/* vdd_log 1200mv is enough for ddr run 666Mhz */
|
/* vdd_log 1200mv is enough for ddr run 666Mhz */
|
||||||
regulate_vdd_log(1200);
|
regulate_vdd_log(1200);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
sdram_init(get_sdram_config());
|
sdram_init(get_sdram_config());
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
|
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
|
||||||
mmu_config_range((uintptr_t)_dram/MiB,
|
mmu_config_range((uintptr_t)_dram/MiB,
|
||||||
|
|
|
@ -64,7 +64,7 @@ static void sdmmc_power_off(void)
|
||||||
|
|
||||||
void main(void)
|
void main(void)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
console_init();
|
console_init();
|
||||||
exception_init();
|
exception_init();
|
||||||
|
@ -77,11 +77,11 @@ void main(void)
|
||||||
/* vdd_log 1200mv is enough for ddr run 666Mhz */
|
/* vdd_log 1200mv is enough for ddr run 666Mhz */
|
||||||
regulate_vdd_log(1200);
|
regulate_vdd_log(1200);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
sdram_init(get_sdram_config());
|
sdram_init(get_sdram_config());
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
|
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
|
||||||
mmu_config_range((uintptr_t)_dram/MiB,
|
mmu_config_range((uintptr_t)_dram/MiB,
|
||||||
|
|
|
@ -1704,7 +1704,7 @@ void sdram_initialize(void)
|
||||||
if (!e7505_mch_is_ready()) {
|
if (!e7505_mch_is_ready()) {
|
||||||
|
|
||||||
/* The real MCH initialisation. */
|
/* The real MCH initialisation. */
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
sdram_set_registers(memctrl);
|
sdram_set_registers(memctrl);
|
||||||
sdram_set_spd_registers(memctrl);
|
sdram_set_spd_registers(memctrl);
|
||||||
|
@ -1713,7 +1713,7 @@ void sdram_initialize(void)
|
||||||
/* Hook for post ECC scrub settings and debug. */
|
/* Hook for post ECC scrub settings and debug. */
|
||||||
sdram_post_ecc(memctrl);
|
sdram_post_ecc(memctrl);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "SDRAM is up.\n");
|
printk(BIOS_DEBUG, "SDRAM is up.\n");
|
||||||
|
|
|
@ -1695,7 +1695,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
|
||||||
|
|
||||||
int ch;
|
int ch;
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
/* Wait for some bit, maybe TXT clear. */
|
/* Wait for some bit, maybe TXT clear. */
|
||||||
if (sysinfo->txt_enabled) {
|
if (sysinfo->txt_enabled) {
|
||||||
|
@ -1803,5 +1803,5 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
|
||||||
raminit_thermal(sysinfo);
|
raminit_thermal(sysinfo);
|
||||||
init_igd(sysinfo);
|
init_igd(sysinfo);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
}
|
}
|
||||||
|
|
|
@ -405,13 +405,13 @@ void perform_raminit(const int s3resume)
|
||||||
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
|
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
|
||||||
pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
|
pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
copy_spd(&pei_data, &spdi);
|
copy_spd(&pei_data, &spdi);
|
||||||
|
|
||||||
sdram_initialize(&pei_data);
|
sdram_initialize(&pei_data);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
post_code(0x3b);
|
post_code(0x3b);
|
||||||
|
|
||||||
|
|
|
@ -1004,7 +1004,7 @@ void __weak disable_spd(void) { }
|
||||||
|
|
||||||
void sdram_initialize(int s3resume)
|
void sdram_initialize(int s3resume)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
enable_spd();
|
enable_spd();
|
||||||
|
|
||||||
dump_spd_registers();
|
dump_spd_registers();
|
||||||
|
@ -1013,5 +1013,5 @@ void sdram_initialize(int s3resume)
|
||||||
sdram_enable();
|
sdram_enable();
|
||||||
|
|
||||||
disable_spd();
|
disable_spd();
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
}
|
}
|
||||||
|
|
|
@ -2683,7 +2683,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
|
||||||
{
|
{
|
||||||
struct sys_info sysinfo;
|
struct sys_info sysinfo;
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
|
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
|
||||||
|
|
||||||
memset(&sysinfo, 0, sizeof(sysinfo));
|
memset(&sysinfo, 0, sizeof(sysinfo));
|
||||||
|
@ -2783,5 +2783,5 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
|
||||||
printk(BIOS_DEBUG, "RAM initialization finished.\n");
|
printk(BIOS_DEBUG, "RAM initialization finished.\n");
|
||||||
|
|
||||||
sdram_setup_processor_side();
|
sdram_setup_processor_side();
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
}
|
}
|
||||||
|
|
|
@ -42,7 +42,7 @@ void mainboard_romstage_entry(void)
|
||||||
|
|
||||||
early_thermal_init();
|
early_thermal_init();
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
chipset_init(s3resume);
|
chipset_init(s3resume);
|
||||||
|
|
||||||
|
@ -52,7 +52,7 @@ void mainboard_romstage_entry(void)
|
||||||
|
|
||||||
raminit(s3resume, spd_addrmap);
|
raminit(s3resume, spd_addrmap);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
intel_early_me_status();
|
intel_early_me_status();
|
||||||
|
|
||||||
|
|
|
@ -50,9 +50,9 @@ void mainboard_romstage_entry(void)
|
||||||
get_mb_spd_addrmap(&spd_addrmap[0]);
|
get_mb_spd_addrmap(&spd_addrmap[0]);
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "Initializing memory\n");
|
printk(BIOS_DEBUG, "Initializing memory\n");
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
sdram_initialize(boot_path, spd_addrmap);
|
sdram_initialize(boot_path, spd_addrmap);
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
printk(BIOS_DEBUG, "Memory initialized\n");
|
printk(BIOS_DEBUG, "Memory initialized\n");
|
||||||
|
|
||||||
post_code(0x31);
|
post_code(0x31);
|
||||||
|
|
|
@ -298,7 +298,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
|
||||||
size_t mrc_size;
|
size_t mrc_size;
|
||||||
ramctr_timing *ctrl_cached = NULL;
|
ramctr_timing *ctrl_cached = NULL;
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
mchbar_setbits32(SAPMCTL, 1 << 0);
|
mchbar_setbits32(SAPMCTL, 1 << 0);
|
||||||
|
|
||||||
|
@ -460,7 +460,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
|
||||||
|
|
||||||
report_memory_config();
|
report_memory_config();
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
cbmem_was_inited = !cbmem_recovery(s3resume);
|
cbmem_was_inited = !cbmem_recovery(s3resume);
|
||||||
if (!fast_boot)
|
if (!fast_boot)
|
||||||
|
|
|
@ -364,9 +364,9 @@ void perform_raminit(int s3resume)
|
||||||
disable_p2p();
|
disable_p2p();
|
||||||
|
|
||||||
pei_data.boot_mode = s3resume ? 2 : 0;
|
pei_data.boot_mode = s3resume ? 2 : 0;
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
sdram_initialize(&pei_data);
|
sdram_initialize(&pei_data);
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
/* Sanity check mrc_var location by verifying a known field */
|
/* Sanity check mrc_var location by verifying a known field */
|
||||||
mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE;
|
mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE;
|
||||||
|
|
|
@ -566,7 +566,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
|
||||||
int fast_boot, cbmem_was_inited;
|
int fast_boot, cbmem_was_inited;
|
||||||
size_t mrc_size;
|
size_t mrc_size;
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
|
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
|
||||||
|
|
||||||
pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
|
pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
|
||||||
|
@ -638,7 +638,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
|
||||||
|
|
||||||
pci_or_config8(HOST_BRIDGE, 0xf4, 1);
|
pci_or_config8(HOST_BRIDGE, 0xf4, 1);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "RAM initialization finished.\n");
|
printk(BIOS_DEBUG, "RAM initialization finished.\n");
|
||||||
|
|
||||||
|
|
|
@ -42,7 +42,7 @@ void vboot_sync_ec(void)
|
||||||
vb2_error_t retval = VB2_SUCCESS;
|
vb2_error_t retval = VB2_SUCCESS;
|
||||||
struct vb2_context *ctx;
|
struct vb2_context *ctx;
|
||||||
|
|
||||||
timestamp_add_now(TS_START_EC_SYNC);
|
timestamp_add_now(TS_EC_SYNC_START);
|
||||||
|
|
||||||
ctx = vboot_get_context();
|
ctx = vboot_get_context();
|
||||||
ctx->flags |= VB2_CONTEXT_EC_SYNC_SUPPORTED;
|
ctx->flags |= VB2_CONTEXT_EC_SYNC_SUPPORTED;
|
||||||
|
@ -84,7 +84,7 @@ void vboot_sync_ec(void)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add_now(TS_END_EC_SYNC);
|
timestamp_add_now(TS_EC_SYNC_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Convert firmware image type into a flash offset */
|
/* Convert firmware image type into a flash offset */
|
||||||
|
|
|
@ -52,10 +52,10 @@ void vboot_run_logic(void)
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n");
|
printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n");
|
||||||
|
|
||||||
timestamp_add_now(TS_START_COPYVER);
|
timestamp_add_now(TS_COPYVER_START);
|
||||||
if (cbfs_prog_stage_load(&verstage))
|
if (cbfs_prog_stage_load(&verstage))
|
||||||
die("failed to load verstage");
|
die("failed to load verstage");
|
||||||
timestamp_add_now(TS_END_COPYVER);
|
timestamp_add_now(TS_COPYVER_END);
|
||||||
|
|
||||||
/* verify and select a slot */
|
/* verify and select a slot */
|
||||||
prog_run(&verstage);
|
prog_run(&verstage);
|
||||||
|
|
|
@ -140,7 +140,7 @@ static vb2_error_t hash_body(struct vb2_context *ctx,
|
||||||
* (This split won't make sense with memory-mapped media like on x86.)
|
* (This split won't make sense with memory-mapped media like on x86.)
|
||||||
*/
|
*/
|
||||||
load_ts = timestamp_get();
|
load_ts = timestamp_get();
|
||||||
timestamp_add(TS_START_HASH_BODY, load_ts);
|
timestamp_add(TS_HASH_BODY_START, load_ts);
|
||||||
|
|
||||||
remaining = region_device_sz(fw_body);
|
remaining = region_device_sz(fw_body);
|
||||||
offset = 0;
|
offset = 0;
|
||||||
|
@ -169,15 +169,15 @@ static vb2_error_t hash_body(struct vb2_context *ctx,
|
||||||
offset += block_size;
|
offset += block_size;
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add(TS_DONE_LOADING, load_ts);
|
timestamp_add(TS_LOADING_END, load_ts);
|
||||||
timestamp_add_now(TS_DONE_HASHING);
|
timestamp_add_now(TS_HASHING_END);
|
||||||
|
|
||||||
/* Check the result (with RSA signature verification) */
|
/* Check the result (with RSA signature verification) */
|
||||||
rv = vb2api_check_hash_get_digest(ctx, hash_digest, hash_digest_sz);
|
rv = vb2api_check_hash_get_digest(ctx, hash_digest, hash_digest_sz);
|
||||||
if (rv)
|
if (rv)
|
||||||
return rv;
|
return rv;
|
||||||
|
|
||||||
timestamp_add_now(TS_END_HASH_BODY);
|
timestamp_add_now(TS_HASH_BODY_END);
|
||||||
|
|
||||||
if (handle_digest_result(hash_digest, hash_digest_sz))
|
if (handle_digest_result(hash_digest, hash_digest_sz))
|
||||||
return VB2_ERROR_UNKNOWN;
|
return VB2_ERROR_UNKNOWN;
|
||||||
|
@ -248,7 +248,7 @@ void verstage_main(void)
|
||||||
struct region_device fw_body;
|
struct region_device fw_body;
|
||||||
vb2_error_t rv;
|
vb2_error_t rv;
|
||||||
|
|
||||||
timestamp_add_now(TS_START_VBOOT);
|
timestamp_add_now(TS_VBOOT_START);
|
||||||
|
|
||||||
/* Lockdown SPI flash controller if required */
|
/* Lockdown SPI flash controller if required */
|
||||||
if (CONFIG(BOOTMEDIA_LOCK_IN_VERSTAGE))
|
if (CONFIG(BOOTMEDIA_LOCK_IN_VERSTAGE))
|
||||||
|
@ -271,12 +271,12 @@ void verstage_main(void)
|
||||||
/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
|
/* Read secdata from TPM. Initialize TPM if secdata not found. We don't
|
||||||
* check the return value here because vb2api_fw_phase1 will catch
|
* check the return value here because vb2api_fw_phase1 will catch
|
||||||
* invalid secdata and tell us what to do (=reboot). */
|
* invalid secdata and tell us what to do (=reboot). */
|
||||||
timestamp_add_now(TS_START_TPMINIT);
|
timestamp_add_now(TS_TPMINIT_START);
|
||||||
if (vboot_setup_tpm(ctx) == TPM_SUCCESS) {
|
if (vboot_setup_tpm(ctx) == TPM_SUCCESS) {
|
||||||
antirollback_read_space_firmware(ctx);
|
antirollback_read_space_firmware(ctx);
|
||||||
antirollback_read_space_kernel(ctx);
|
antirollback_read_space_kernel(ctx);
|
||||||
}
|
}
|
||||||
timestamp_add_now(TS_END_TPMINIT);
|
timestamp_add_now(TS_TPMINIT_END);
|
||||||
|
|
||||||
if (get_recovery_mode_switch()) {
|
if (get_recovery_mode_switch()) {
|
||||||
ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
|
ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
|
||||||
|
@ -343,9 +343,9 @@ void verstage_main(void)
|
||||||
|
|
||||||
/* Try that slot (verify its keyblock and preamble) */
|
/* Try that slot (verify its keyblock and preamble) */
|
||||||
printk(BIOS_INFO, "Phase 3\n");
|
printk(BIOS_INFO, "Phase 3\n");
|
||||||
timestamp_add_now(TS_START_VERIFY_SLOT);
|
timestamp_add_now(TS_VERIFY_SLOT_START);
|
||||||
rv = vb2api_fw_phase3(ctx);
|
rv = vb2api_fw_phase3(ctx);
|
||||||
timestamp_add_now(TS_END_VERIFY_SLOT);
|
timestamp_add_now(TS_VERIFY_SLOT_END);
|
||||||
if (rv) {
|
if (rv) {
|
||||||
printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
|
printk(BIOS_INFO, "Reboot requested (%x)\n", rv);
|
||||||
vboot_save_data(ctx);
|
vboot_save_data(ctx);
|
||||||
|
@ -367,7 +367,7 @@ void verstage_main(void)
|
||||||
|
|
||||||
/* Only extend PCRs once on boot. */
|
/* Only extend PCRs once on boot. */
|
||||||
if (!(ctx->flags & VB2_CONTEXT_S3_RESUME)) {
|
if (!(ctx->flags & VB2_CONTEXT_S3_RESUME)) {
|
||||||
timestamp_add_now(TS_START_TPMPCR);
|
timestamp_add_now(TS_TPMPCR_START);
|
||||||
rv = extend_pcrs(ctx);
|
rv = extend_pcrs(ctx);
|
||||||
if (rv) {
|
if (rv) {
|
||||||
printk(BIOS_WARNING,
|
printk(BIOS_WARNING,
|
||||||
|
@ -376,12 +376,12 @@ void verstage_main(void)
|
||||||
vboot_save_data(ctx);
|
vboot_save_data(ctx);
|
||||||
vboot_reboot();
|
vboot_reboot();
|
||||||
}
|
}
|
||||||
timestamp_add_now(TS_END_TPMPCR);
|
timestamp_add_now(TS_TPMPCR_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Lock TPM */
|
/* Lock TPM */
|
||||||
|
|
||||||
timestamp_add_now(TS_START_TPMLOCK);
|
timestamp_add_now(TS_TPMLOCK_START);
|
||||||
rv = antirollback_lock_space_firmware();
|
rv = antirollback_lock_space_firmware();
|
||||||
if (rv) {
|
if (rv) {
|
||||||
printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
|
printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv);
|
||||||
|
@ -389,7 +389,7 @@ void verstage_main(void)
|
||||||
vboot_save_data(ctx);
|
vboot_save_data(ctx);
|
||||||
vboot_reboot();
|
vboot_reboot();
|
||||||
}
|
}
|
||||||
timestamp_add_now(TS_END_TPMLOCK);
|
timestamp_add_now(TS_TPMLOCK_END);
|
||||||
|
|
||||||
/* Lock rec hash space if available. */
|
/* Lock rec hash space if available. */
|
||||||
if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) {
|
if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) {
|
||||||
|
@ -408,5 +408,5 @@ void verstage_main(void)
|
||||||
vboot_is_firmware_slot_a(ctx) ? 'A' : 'B');
|
vboot_is_firmware_slot_a(ctx) ? 'A' : 'B');
|
||||||
|
|
||||||
verstage_main_exit:
|
verstage_main_exit:
|
||||||
timestamp_add_now(TS_END_VBOOT);
|
timestamp_add_now(TS_VBOOT_END);
|
||||||
}
|
}
|
||||||
|
|
|
@ -12,7 +12,7 @@
|
||||||
|
|
||||||
asmlinkage void car_stage_entry(void)
|
asmlinkage void car_stage_entry(void)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
post_code(0x40);
|
post_code(0x40);
|
||||||
|
|
||||||
|
|
|
@ -171,7 +171,7 @@ static void soc_update_apob_cache(void *unused)
|
||||||
printk(BIOS_DEBUG, "APOB valid copy is already in flash\n");
|
printk(BIOS_DEBUG, "APOB valid copy is already in flash\n");
|
||||||
|
|
||||||
if (!update_needed) {
|
if (!update_needed) {
|
||||||
timestamp_add_now(TS_AMD_APOB_DONE);
|
timestamp_add_now(TS_AMD_APOB_END);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -199,7 +199,7 @@ static void soc_update_apob_cache(void *unused)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add_now(TS_AMD_APOB_DONE);
|
timestamp_add_now(TS_AMD_APOB_END);
|
||||||
|
|
||||||
printk(BIOS_INFO, "Updated APOB in flash\n");
|
printk(BIOS_INFO, "Updated APOB in flash\n");
|
||||||
}
|
}
|
||||||
|
|
|
@ -102,7 +102,7 @@ static AGESA_STATUS amd_init_reset(AMD_RESET_PARAMS *ResetParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_RESET_START);
|
timestamp_add_now(TS_AGESA_INIT_RESET_START);
|
||||||
status = amd_dispatch(ResetParams);
|
status = amd_dispatch(ResetParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_RESET_DONE);
|
timestamp_add_now(TS_AGESA_INIT_RESET_END);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
@ -116,7 +116,7 @@ static AGESA_STATUS amd_init_early(AMD_EARLY_PARAMS *EarlyParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_EARLY_START);
|
timestamp_add_now(TS_AGESA_INIT_EARLY_START);
|
||||||
status = amd_dispatch(EarlyParams);
|
status = amd_dispatch(EarlyParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_EARLY_DONE);
|
timestamp_add_now(TS_AGESA_INIT_EARLY_END);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
@ -173,7 +173,7 @@ static AGESA_STATUS amd_init_post(AMD_POST_PARAMS *PostParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_POST_START);
|
timestamp_add_now(TS_AGESA_INIT_POST_START);
|
||||||
status = amd_dispatch(PostParams);
|
status = amd_dispatch(PostParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_POST_DONE);
|
timestamp_add_now(TS_AGESA_INIT_POST_END);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* AGESA passes back the base and size of UMA. This is the only
|
* AGESA passes back the base and size of UMA. This is the only
|
||||||
|
@ -208,7 +208,7 @@ static AGESA_STATUS amd_init_env(AMD_ENV_PARAMS *EnvParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_ENV_START);
|
timestamp_add_now(TS_AGESA_INIT_ENV_START);
|
||||||
status = amd_dispatch(EnvParams);
|
status = amd_dispatch(EnvParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_ENV_DONE);
|
timestamp_add_now(TS_AGESA_INIT_ENV_END);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
@ -251,7 +251,7 @@ static AGESA_STATUS amd_init_mid(AMD_MID_PARAMS *MidParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_MID_START);
|
timestamp_add_now(TS_AGESA_INIT_MID_START);
|
||||||
status = amd_dispatch(MidParams);
|
status = amd_dispatch(MidParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_MID_DONE);
|
timestamp_add_now(TS_AGESA_INIT_MID_END);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
@ -268,7 +268,7 @@ static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_LATE_START);
|
timestamp_add_now(TS_AGESA_INIT_LATE_START);
|
||||||
Status = amd_dispatch(LateParams);
|
Status = amd_dispatch(LateParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_LATE_DONE);
|
timestamp_add_now(TS_AGESA_INIT_LATE_END);
|
||||||
|
|
||||||
DmiTable = LateParams->DmiTable;
|
DmiTable = LateParams->DmiTable;
|
||||||
AcpiPstate = LateParams->AcpiPState;
|
AcpiPstate = LateParams->AcpiPState;
|
||||||
|
@ -295,7 +295,7 @@ static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_RTB_START);
|
timestamp_add_now(TS_AGESA_INIT_RTB_START);
|
||||||
Status = amd_dispatch(RtbParams);
|
Status = amd_dispatch(RtbParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_RTB_DONE);
|
timestamp_add_now(TS_AGESA_INIT_RTB_END);
|
||||||
|
|
||||||
if (Status != AGESA_SUCCESS)
|
if (Status != AGESA_SUCCESS)
|
||||||
return Status;
|
return Status;
|
||||||
|
@ -314,7 +314,7 @@ static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_INIT_RESUME_START);
|
timestamp_add_now(TS_AGESA_INIT_RESUME_START);
|
||||||
status = amd_dispatch(InitResumeParams);
|
status = amd_dispatch(InitResumeParams);
|
||||||
timestamp_add_now(TS_AGESA_INIT_RESUME_DONE);
|
timestamp_add_now(TS_AGESA_INIT_RESUME_END);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
@ -329,7 +329,7 @@ static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_S3_LATE_START);
|
timestamp_add_now(TS_AGESA_S3_LATE_START);
|
||||||
Status = amd_dispatch(S3LateParams);
|
Status = amd_dispatch(S3LateParams);
|
||||||
timestamp_add_now(TS_AGESA_S3_LATE_DONE);
|
timestamp_add_now(TS_AGESA_S3_LATE_END);
|
||||||
|
|
||||||
return Status;
|
return Status;
|
||||||
}
|
}
|
||||||
|
@ -342,7 +342,7 @@ static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams)
|
||||||
|
|
||||||
timestamp_add_now(TS_AGESA_S3_FINAL_START);
|
timestamp_add_now(TS_AGESA_S3_FINAL_START);
|
||||||
Status = amd_dispatch(S3FinalParams);
|
Status = amd_dispatch(S3FinalParams);
|
||||||
timestamp_add_now(TS_AGESA_S3_FINAL_DONE);
|
timestamp_add_now(TS_AGESA_S3_FINAL_END);
|
||||||
|
|
||||||
return Status;
|
return Status;
|
||||||
}
|
}
|
||||||
|
|
|
@ -13,7 +13,7 @@
|
||||||
|
|
||||||
asmlinkage void car_stage_entry(void)
|
asmlinkage void car_stage_entry(void)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
post_code(0x40);
|
post_code(0x40);
|
||||||
|
|
||||||
|
|
|
@ -14,7 +14,7 @@
|
||||||
|
|
||||||
asmlinkage void car_stage_entry(void)
|
asmlinkage void car_stage_entry(void)
|
||||||
{
|
{
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
post_code(0x40);
|
post_code(0x40);
|
||||||
|
|
||||||
|
|
|
@ -137,9 +137,9 @@ void mainboard_romstage_entry(void)
|
||||||
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
|
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
|
||||||
|
|
||||||
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) {
|
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) {
|
||||||
timestamp_add_now(TS_START_CSE_FW_SYNC);
|
timestamp_add_now(TS_CSE_FW_SYNC_START);
|
||||||
cse_fw_sync();
|
cse_fw_sync();
|
||||||
timestamp_add_now(TS_END_CSE_FW_SYNC);
|
timestamp_add_now(TS_CSE_FW_SYNC_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -101,7 +101,7 @@ void mainboard_romstage_entry(void)
|
||||||
memset(&mp, 0, sizeof(mp));
|
memset(&mp, 0, sizeof(mp));
|
||||||
mainboard_fill_mrc_params(&mp);
|
mainboard_fill_mrc_params(&mp);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
ps = fill_power_state();
|
ps = fill_power_state();
|
||||||
prev_sleep_state = chipset_prev_sleep_state(ps);
|
prev_sleep_state = chipset_prev_sleep_state(ps);
|
||||||
|
@ -115,7 +115,7 @@ void mainboard_romstage_entry(void)
|
||||||
/* Initialize RAM */
|
/* Initialize RAM */
|
||||||
raminit(&mp, prev_sleep_state);
|
raminit(&mp, prev_sleep_state);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
romstage_handoff_init(s3resume);
|
romstage_handoff_init(s3resume);
|
||||||
}
|
}
|
||||||
|
|
|
@ -188,14 +188,14 @@ void perform_raminit(const struct chipset_power_state *const power_state)
|
||||||
|
|
||||||
post_code(0x32);
|
post_code(0x32);
|
||||||
|
|
||||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
timestamp_add_now(TS_INITRAM_START);
|
||||||
|
|
||||||
pei_data.boot_mode = power_state->prev_sleep_state;
|
pei_data.boot_mode = power_state->prev_sleep_state;
|
||||||
|
|
||||||
/* Initialize RAM */
|
/* Initialize RAM */
|
||||||
sdram_initialize(&pei_data);
|
sdram_initialize(&pei_data);
|
||||||
|
|
||||||
timestamp_add_now(TS_AFTER_INITRAM);
|
timestamp_add_now(TS_INITRAM_END);
|
||||||
|
|
||||||
int cbmem_was_initted = !cbmem_recovery(s3resume);
|
int cbmem_was_initted = !cbmem_recovery(s3resume);
|
||||||
if (s3resume && !cbmem_was_initted) {
|
if (s3resume && !cbmem_was_initted) {
|
||||||
|
|
|
@ -192,9 +192,9 @@ static void do_send_end_of_post(void)
|
||||||
|
|
||||||
set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
|
set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
|
||||||
|
|
||||||
timestamp_add_now(TS_ME_BEFORE_END_OF_POST);
|
timestamp_add_now(TS_ME_END_OF_POST_START);
|
||||||
handle_cse_eop_result(cse_send_eop());
|
handle_cse_eop_result(cse_send_eop());
|
||||||
timestamp_add_now(TS_ME_AFTER_END_OF_POST);
|
timestamp_add_now(TS_ME_END_OF_POST_END);
|
||||||
|
|
||||||
set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);
|
set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);
|
||||||
|
|
||||||
|
|
|
@ -166,7 +166,7 @@ int intel_early_me_init_done(u8 status)
|
||||||
"ME: ME is reporting as disabled, "
|
"ME: ME is reporting as disabled, "
|
||||||
"so not waiting for a response.\n");
|
"so not waiting for a response.\n");
|
||||||
} else {
|
} else {
|
||||||
timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
|
timestamp_add_now(TS_ME_INFORM_DRAM_START);
|
||||||
udelay(100);
|
udelay(100);
|
||||||
millisec = 0;
|
millisec = 0;
|
||||||
do {
|
do {
|
||||||
|
@ -177,7 +177,7 @@ int intel_early_me_init_done(u8 status)
|
||||||
millisec++;
|
millisec++;
|
||||||
} while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK)
|
} while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK)
|
||||||
&& (millisec <= 5000));
|
&& (millisec <= 5000));
|
||||||
timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
|
timestamp_add_now(TS_ME_INFORM_DRAM_END);
|
||||||
}
|
}
|
||||||
|
|
||||||
me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
|
me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
|
||||||
|
|
|
@ -89,7 +89,7 @@ static void enable_update(void *unused)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
timestamp_add_now(TS_START_TPM_ENABLE_UPDATE);
|
timestamp_add_now(TS_TPM_ENABLE_UPDATE_START);
|
||||||
|
|
||||||
/* Reboot in 1000 ms if necessary. */
|
/* Reboot in 1000 ms if necessary. */
|
||||||
ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS,
|
ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS,
|
||||||
|
@ -117,7 +117,7 @@ static void enable_update(void *unused)
|
||||||
*/
|
*/
|
||||||
cr50_reset_reqd = cr50_is_reset_needed();
|
cr50_reset_reqd = cr50_is_reset_needed();
|
||||||
if (!cr50_reset_reqd) {
|
if (!cr50_reset_reqd) {
|
||||||
timestamp_add_now(TS_END_TPM_ENABLE_UPDATE);
|
timestamp_add_now(TS_TPM_ENABLE_UPDATE_END);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -25,7 +25,7 @@ void test_timestamp_add(void **state)
|
||||||
|
|
||||||
timestamp_init(timestamp_base);
|
timestamp_init(timestamp_base);
|
||||||
|
|
||||||
timestamp_add(TS_START_ROMSTAGE, base_multipler);
|
timestamp_add(TS_ROMSTAGE_START, base_multipler);
|
||||||
|
|
||||||
assert_int_equal(1, glob_ts_table->num_entries);
|
assert_int_equal(1, glob_ts_table->num_entries);
|
||||||
|
|
||||||
|
@ -61,7 +61,7 @@ void test_timestamp_add_now(void **state)
|
||||||
|
|
||||||
dummy_timestamp_set(base_multipler);
|
dummy_timestamp_set(base_multipler);
|
||||||
|
|
||||||
timestamp_add_now(TS_START_ROMSTAGE);
|
timestamp_add_now(TS_ROMSTAGE_START);
|
||||||
|
|
||||||
assert_int_equal(1, glob_ts_table->num_entries);
|
assert_int_equal(1, glob_ts_table->num_entries);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue