From ad6c407927a2aa05cb7ecb47c833b230c227db36 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 21 Dec 2022 11:41:33 +0530 Subject: [PATCH] soc/intel/meteorlake: Disable L1 substates for PCIe compliance test mode Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. This patch is backported from commit 8c46232005767ecbdebb7290f15cacf2756c9586 (soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode). Signed-off-by: Subrata Banik Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Ivy Jian --- src/soc/intel/meteorlake/fsp_params.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index a624025591..ad6db109e4 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -86,7 +86,9 @@ static const pci_devfn_t uart_dev[] = { */ static int get_l1_substate_control(enum L1_substates_control ctl) { - if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) + ctl = L1_SS_DISABLED; + else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) ctl = L1_SS_L1_2; return ctl - 1; }