rk3399: set proper configuration of SDMMC interface
For proper interface operation the drive strength on all pins is set to 8 mA and all pull ups/pull downs disabled, this matches the current kernel configuration. BRANCH=none BUG=chrome-os-partner:53257 TEST=it is possible to boot Chrome OS on Gru from various micro SD cards which were failing to boot before. Change-Id: Ie43e52a52cd0513d48d0ecc8ac02fbb100baf9a4 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 6bb0549ed728ac3c5faab6cbe16e2487400e67ed Original-Change-Id: I5180537d3ceb74a9a2f7b3982ca94d3e2daf0369 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344491 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14853 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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@ -33,6 +33,39 @@ static void configure_sdmmc(void)
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gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */
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/*
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* The SD card on this board is connected to port SDMMC0, which is
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* multiplexed with GPIO4B pins 0..5.
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*
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* Disable all pullups on these pins. For pullup configuration
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* register layout stacks banks 2 through 4 together, hence [2] means
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* group 4, [1] means bank B. This register is described on page 342
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* of section 1 of the TRM.
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*
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* Each GPIO pin's pull config takes two bits, writing zero to the
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* field disables pull ups/downs, as described on page 342 of rk3399
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* TRM Version 0.3 Part 1.
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*/
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write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0));
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/*
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* Set all outputs' drive strength to 8 mA. Group 4 bank B driver
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* strength requires three bits per pin. Value of 2 written in that
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* three bit field means '8 mA', as deduced from the kernel code.
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*
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* Thus the six pins involved in SDMMC interface require 18 bits to
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* configure drive strength, but each 32 bit register provides only 16
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* bits for this setting, this covers 5 pins fully and one bit from
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* the 6th pin. Two more bits spill over to the next register. This is
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* described on page 378 of rk3399 TRM Version 0.3 Part 1.
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*/
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write32(&rk3399_grf->gpio4b_e01,
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RK_CLRSETBITS(0xffff,
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(2 << 0) | (2 << 3) |
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(2 << 6) | (2 << 9) | (2 << 12)));
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write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1));
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/* And now set the multiplexor to enable SDMMC0. */
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write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC);
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}
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