intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -15,7 +15,6 @@
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#include <stdint.h>
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#include <cf9_reset.h>
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#include <delay.h>
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#include <console/console.h>
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#include <arch/romstage.h>
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#include <cpu/x86/lapic.h>
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@ -246,10 +245,8 @@ void mainboard_romstage_entry(void)
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enable_lapic();
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/* Force PCIRST# */
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pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
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udelay(200 * 1000);
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pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
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/* Force PCIRST# to conventional PCI slot and Firewire. */
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ich7_p2p_secondary_reset();
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ich7_enable_lpc();
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early_superio_config_w83627thg();
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@ -17,7 +17,6 @@
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#include <stdint.h>
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#include <arch/io.h>
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#include <cf9_reset.h>
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#include <delay.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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@ -209,10 +208,8 @@ void mainboard_romstage_entry(void)
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enable_lapic();
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/* Force PCIRST# */
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pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
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udelay(200 * 1000);
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pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
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/* Force PCIRST# to cardbus add-on. */
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ich7_p2p_secondary_reset();
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ich7_enable_lpc();
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early_superio_config();
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@ -17,6 +17,8 @@
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cbmem.h>
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@ -549,14 +551,9 @@ static void i945_setup_pci_express_x16(void)
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* PCI bus 0x0a and check whether we find a device on 0:a.0
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*/
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/* First we reset the secondary bus */
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reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
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reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
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/* Read back and clear reset bit. */
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reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
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reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */
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pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
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/* Force PCIRST# */
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pci_s_assert_secondary_reset(p2peg);
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pci_s_deassert_secondary_reset(p2peg);
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reg16 = pci_read_config16(p2peg, SLOTSTS);
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printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
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@ -565,10 +562,7 @@ static void i945_setup_pci_express_x16(void)
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reg16 |= (1 << 4) | (1 << 0);
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pci_write_config16(p2peg, SLOTSTS, reg16);
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pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00);
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pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00);
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pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary);
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pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary);
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pci_s_bridge_set_secondary(p2peg, tmp_secondary);
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reg32 = pci_read_config32(p2peg, 0x224);
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reg32 &= ~(1 << 8);
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@ -614,11 +608,9 @@ static void i945_setup_pci_express_x16(void)
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reg32 |= 1;
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pci_write_config32(p2peg, PEGSTS, reg32);
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reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
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reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
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reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
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/* Force PCIRST# */
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pci_s_assert_secondary_reset(p2peg);
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pci_s_deassert_secondary_reset(p2peg);
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printk(BIOS_DEBUG, "PCIe link training ...");
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timeout = 0x7ffff;
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@ -774,17 +766,14 @@ disable_pciexpress_x16_link:
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MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
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reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
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reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
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/* Toggle PCIRST# */
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pci_s_assert_secondary_reset(p2peg);
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reg32 = pci_read_config32(p2peg, 0x224);
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reg32 |= (1 << 8);
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pci_write_config32(p2peg, 0x224, reg32);
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reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
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reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
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pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
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pci_s_deassert_secondary_reset(p2peg);
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printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
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timeout = 0x7fffff;
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@ -880,6 +869,14 @@ static void ich7_setup_pci_express(void)
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pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
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}
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void ich7_p2p_secondary_reset(void)
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{
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pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0);
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pci_s_assert_secondary_reset(p2p_bridge);
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mdelay(200);
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pci_s_deassert_secondary_reset(p2p_bridge);
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}
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void i945_early_initialization(void)
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{
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/* Print some chipset specific information */
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@ -83,8 +83,6 @@
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/* Device 0:1.0 PCI configuration space (PCI Express) */
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#define PCISTS1 0x06 /* 16bit */
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#define SBUSN1 0x19 /* 8bit */
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#define SUBUSN1 0x1a /* 8bit */
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#define SSTS1 0x1e /* 16bit */
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#define PEG_CAP 0xa2 /* 16bit */
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#define DSTS 0xaa /* 16bit */
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@ -39,6 +39,8 @@
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void i82801gx_enable(struct device *dev);
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#endif
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void ich7_p2p_secondary_reset(void);
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void enable_smbus(void);
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#if ENV_ROMSTAGE
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