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intel/i945,i82801gx: Refactor early PCI bridge reset 

Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-09-30 04:14:19 +03:00
parent 81ade745b1
commit ad787e18e0
5 changed files with 26 additions and 35 deletions
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7
src/mainboard/kontron/986lcd-m/romstage.c
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@ -15,7 +15,6 @@
#include <stdint.h> #include <stdint.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <delay.h>
#include <console/console.h> #include <console/console.h>
#include <arch/romstage.h> #include <arch/romstage.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
@ -246,10 +245,8 @@ void mainboard_romstage_entry(void)
enable_lapic(); enable_lapic();
/* Force PCIRST# */ /* Force PCIRST# to conventional PCI slot and Firewire. */
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); ich7_p2p_secondary_reset();
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
ich7_enable_lpc(); ich7_enable_lpc();
early_superio_config_w83627thg(); early_superio_config_w83627thg();

7
src/mainboard/roda/rk886ex/romstage.c
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@ -17,7 +17,6 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <delay.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -209,10 +208,8 @@ void mainboard_romstage_entry(void)
enable_lapic(); enable_lapic();
/* Force PCIRST# */ /* Force PCIRST# to cardbus add-on. */
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); ich7_p2p_secondary_reset();
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
ich7_enable_lpc(); ich7_enable_lpc();
early_superio_config(); early_superio_config();

43
src/northbridge/intel/i945/early_init.c
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@ -17,6 +17,8 @@
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h> #include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include <delay.h>
#include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cbmem.h> #include <cbmem.h>
@ -549,14 +551,9 @@ static void i945_setup_pci_express_x16(void)
* PCI bus 0x0a and check whether we find a device on 0:a.0 * PCI bus 0x0a and check whether we find a device on 0:a.0
*/ */
/* First we reset the secondary bus */ /* Force PCIRST# */
reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); pci_s_assert_secondary_reset(p2peg);
reg16 |= PCI_BRIDGE_CTL_BUS_RESET; pci_s_deassert_secondary_reset(p2peg);
pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
/* Read back and clear reset bit. */
reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */
pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
reg16 = pci_read_config16(p2peg, SLOTSTS); reg16 = pci_read_config16(p2peg, SLOTSTS);
printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
@ -565,10 +562,7 @@ static void i945_setup_pci_express_x16(void)
reg16 |= (1 << 4) | (1 << 0); reg16 |= (1 << 4) | (1 << 0);
pci_write_config16(p2peg, SLOTSTS, reg16); pci_write_config16(p2peg, SLOTSTS, reg16);
pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); pci_s_bridge_set_secondary(p2peg, tmp_secondary);
pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00);
pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary);
pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary);
reg32 = pci_read_config32(p2peg, 0x224); reg32 = pci_read_config32(p2peg, 0x224);
reg32 &= ~(1 << 8); reg32 &= ~(1 << 8);
@ -614,11 +608,9 @@ static void i945_setup_pci_express_x16(void)
reg32 |= 1; reg32 |= 1;
pci_write_config32(p2peg, PEGSTS, reg32); pci_write_config32(p2peg, PEGSTS, reg32);
reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); /* Force PCIRST# */
reg16 |= PCI_BRIDGE_CTL_BUS_RESET; pci_s_assert_secondary_reset(p2peg);
pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); pci_s_deassert_secondary_reset(p2peg);
reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
printk(BIOS_DEBUG, "PCIe link training ..."); printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff; timeout = 0x7ffff;
@ -774,17 +766,14 @@ disable_pciexpress_x16_link:
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); /* Toggle PCIRST# */
reg16 |= PCI_BRIDGE_CTL_BUS_RESET; pci_s_assert_secondary_reset(p2peg);
pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
reg32 = pci_read_config32(p2peg, 0x224); reg32 = pci_read_config32(p2peg, 0x224);
reg32 |= (1 << 8); reg32 |= (1 << 8);
pci_write_config32(p2peg, 0x224, reg32); pci_write_config32(p2peg, 0x224, reg32);
reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); pci_s_deassert_secondary_reset(p2peg);
reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
printk(BIOS_DEBUG, "Wait for link to enter detect state... "); printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff; timeout = 0x7fffff;
@ -880,6 +869,14 @@ static void ich7_setup_pci_express(void)
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
} }
void ich7_p2p_secondary_reset(void)
{
pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0);
pci_s_assert_secondary_reset(p2p_bridge);
mdelay(200);
pci_s_deassert_secondary_reset(p2p_bridge);
}
void i945_early_initialization(void) void i945_early_initialization(void)
{ {
/* Print some chipset specific information */ /* Print some chipset specific information */

2
src/northbridge/intel/i945/i945.h
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@ -83,8 +83,6 @@
/* Device 0:1.0 PCI configuration space (PCI Express) */ /* Device 0:1.0 PCI configuration space (PCI Express) */
#define PCISTS1 0x06 /* 16bit */ #define PCISTS1 0x06 /* 16bit */
#define SBUSN1 0x19 /* 8bit */
#define SUBUSN1 0x1a /* 8bit */
#define SSTS1 0x1e /* 16bit */ #define SSTS1 0x1e /* 16bit */
#define PEG_CAP 0xa2 /* 16bit */ #define PEG_CAP 0xa2 /* 16bit */
#define DSTS 0xaa /* 16bit */ #define DSTS 0xaa /* 16bit */

2
src/southbridge/intel/i82801gx/i82801gx.h
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@ -39,6 +39,8 @@
void i82801gx_enable(struct device *dev); void i82801gx_enable(struct device *dev);
#endif #endif
void ich7_p2p_secondary_reset(void);
void enable_smbus(void); void enable_smbus(void);
#if ENV_ROMSTAGE #if ENV_ROMSTAGE