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soc/amd/cezanne: Add support to perform early EC sync 

Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also
help cr50 to set the boot mode as NORMAL instead of NO_BOOT.

BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash()            Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)

Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-03-31 17:49:38 -06:00 committed by Raul Rangel
parent 0f4191204b
commit ad7c33abd2
1 changed files with 4 additions and 0 deletions
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4
src/soc/amd/cezanne/romstage.c
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@ -8,12 +8,16 @@
#include <console/console.h> #include <console/console.h>
#include <fsp/api.h> #include <fsp/api.h>
#include <program_loading.h> #include <program_loading.h>
#include <security/vboot/vboot_common.h>
asmlinkage void car_stage_entry(void) asmlinkage void car_stage_entry(void)
{ {
post_code(0x40); post_code(0x40);
console_init(); console_init();
if (CONFIG(VBOOT_EARLY_EC_SYNC))
vboot_sync_ec();
post_code(0x41); post_code(0x41);
fsp_memory_init(acpi_is_wakeup_s3()); fsp_memory_init(acpi_is_wakeup_s3());