mb/google/guybrush: Enable Chrome EC

BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mathew King 2021-02-23 13:08:15 -07:00 committed by Felix Held
parent 15c4345cfd
commit ad83023425
6 changed files with 76 additions and 2 deletions

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@ -9,14 +9,14 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select FW_CONFIG
select MAINBOARD_HAS_CHROMEOS
select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_USE_ESPI
config CHROMEOS
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_SWITCHES
config VBOOT

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@ -3,6 +3,7 @@
bootblock-y += bootblock.c
ramstage-y += mainboard.c
ramstage-y += ec.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
subdirs-y += variants/baseboard

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@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <amdblocks/gpio_banks.h>
#include <amdblocks/smi.h>
#include <ec/google/chromeec/ec.h>
#include <variant/ec.h>
void mainboard_ec_init(void)
{
const struct google_chromeec_event_info info = {
.log_events = MAINBOARD_EC_LOG_EVENTS,
.sci_events = MAINBOARD_EC_SCI_EVENTS,
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
};
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
}

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@ -2,6 +2,7 @@
#include <baseboard/variants.h>
#include <device/device.h>
#include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_configure_gpios(void)
@ -19,6 +20,7 @@ static void mainboard_configure_gpios(void)
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
mainboard_ec_init();
}
static void mainboard_enable(struct device *dev)

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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __MAINBOARD_EC_H__
#define __MAINBOARD_EC_H__
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid, power button or mode change event */
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) \
| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#endif /* __MAINBOARD_EC_H__ */

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@ -0,0 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/ec.h>