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soc/intel/braswell: Populate NVS SCC BAR1 

Cherry-pick from Chromium commit f92d7be.

This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put
SD controller in D3

Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org>

Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Hannah Williams 2017-03-21 22:34:01 -07:00 committed by Martin Roth
parent aec5e663eb
commit ad8669ef30
1 changed files with 4 additions and 1 deletions
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5
src/soc/intel/braswell/scc.c
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@ -42,7 +42,10 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
/* Save BAR0 and BAR1 to ACPI NVS */ /* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0); bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar) if (bar)
gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; gnvs->dev.scc_bar0[nvs_index] = bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_2);
if (bar)
gnvs->dev.scc_bar1[nvs_index] = bar->base;
/* Device is enabled in ACPI mode */ /* Device is enabled in ACPI mode */
gnvs->dev.scc_en[nvs_index] = 1; gnvs->dev.scc_en[nvs_index] = 1;