exynos5420: Fix the clock divisor mask

The divisor mask had been set to 0xff, but the bitfield is 4 bits wide.

Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4384
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/cpu/samsung/exynos5420/clock.c

@@ -359,7 +359,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
 {
 	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned shift;
-	unsigned mask = 0xff;
+	unsigned mask = 0xf;
 	u32 *reg;
 
 	switch (periph_id) {