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exynos5420: Fix the clock divisor mask 

The divisor mask had been set to 0xff, but the bitfield is 4 bits wide.

Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4384
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Gabe Black 2013-07-24 04:06:37 -07:00 committed by Patrick Georgi
parent dd8f60363a
commit ad88fda1cf
1 changed files with 1 additions and 1 deletions
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src/cpu/samsung/exynos5420/clock.c
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@ -359,7 +359,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
{ {
struct exynos5420_clock *clk = samsung_get_base_clock(); struct exynos5420_clock *clk = samsung_get_base_clock();
unsigned shift; unsigned shift;
unsigned mask = 0xff; unsigned mask = 0xf;
u32 *reg; u32 *reg;
switch (periph_id) { switch (periph_id) {