Get rid of a few more warnings.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/arima/hdama/romstage.c

@@ -1,10 +1,10 @@
 #include <stdint.h>
+#include <string.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"

src/mainboard/pcengines/alix1c/romstage.c

@@ -36,7 +36,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
-void cs5536_enable_smbus(void)
+static void cs5536_enable_smbus(void)
 {
 }
 

src/northbridge/amd/amdfam10/Makefile.inc

@@ -10,4 +10,3 @@ obj-$(CONFIG_GENERATE_ACPI_TABLES) += sspr4.o
 obj-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.o
 
 obj-y += get_pci1234.o
-

src/northbridge/amd/amdfam10/debug.c

@@ -26,7 +26,7 @@
 
 static inline void print_debug_addr(const char *str, void *val)
 {
-#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1
 		printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
 #endif
 }

src/northbridge/amd/amdfam10/get_pci1234.c

@@ -55,6 +55,7 @@
  *
  */
 
+#include "northbridge.h"
 
 void get_pci1234(void)
 {

src/northbridge/amd/amdfam10/northbridge.h

@@ -21,5 +21,6 @@
 #define NORTHBRIDGE_AMD_AMDFAM10_H
 
 u32 amdfam10_scan_root_bus(device_t root, u32 max);
+void get_pci1234(void);
 
 #endif /* NORTHBRIDGE_AMD_AMDFAM10_H */

src/northbridge/amd/amdk8/raminit_f.c

@@ -2511,9 +2511,8 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 	unsigned SlowAccessMode = 0;
 #endif
 
-	long dimm_mask = meminfo->dimm_mask & 0x0f;
-
 #if CONFIG_DIMM_SUPPORT==0x0104   /* DDR2 and REG */
+	long dimm_mask = meminfo->dimm_mask & 0x0f;
 	/* for REG DIMM */
 	dword = 0x00111222;
 	dwordx = 0x002f0000;
@@ -2578,6 +2577,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 #endif
 
 #if CONFIG_DIMM_SUPPORT==0x0004  /* DDR2 and unbuffered */
+	long dimm_mask = meminfo->dimm_mask & 0x0f;
 	/* for UNBUF DIMM */
 	dword = 0x00111222;
 	dwordx = 0x002f2f00;

src/northbridge/amd/amdk8/raminit_f_dqs.c

@@ -528,7 +528,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
 	unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
-	unsigned cpu_f0_f1;
+	unsigned cpu_f0_f1 = 0;
 #endif
 
 	if(Pass == DQS_FIRST_PASS) {

src/northbridge/amd/amdmct/mct/mct_d.c

@@ -42,8 +42,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstatA);
 static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 					struct DCTStatStruc *pDCTstatA);
-static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat,
-				struct DCTStatStruc *pDCTstatA);
 static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstatA);
 static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
@@ -477,6 +475,8 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 }
 
 #ifdef UNUSED_CODE
+static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat,
+				struct DCTStatStruc *pDCTstatA);
 static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstatA)
 {

src/northbridge/intel/i3100/raminit.c

@@ -944,7 +944,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	u32 drc;
 	u32 data32;
 	u32 mode_reg;
-	u32 *iptr;
+	u32 const *iptr;
 	u16 data16;
 	static const struct {
 		u32 clkgr[4];

src/northbridge/via/vx800/vga.c

@@ -126,6 +126,7 @@ static int via_vx800_int15_handler(struct eregs *regs)
 	return res;
 }
 
+#ifdef UNUSED_CODE
 void write_protect_vgabios(void)
 {
 	device_t dev;
@@ -141,6 +142,7 @@ void write_protect_vgabios(void)
 	   //if(dev)
 	   //   pci_write_config8(dev, 0x61, 0xff); */
 }
+#endif
 
 extern u8 acpi_sleep_type;
 static void vga_init(device_t dev)

src/southbridge/intel/esb6300/esb6300_smbus.h

@@ -14,6 +14,8 @@
 
 #define SMBUS_TIMEOUT (100*1000*10)
 
+#include <delay.h>
+
 static int smbus_wait_until_ready(unsigned smbus_io_base)
 {
 	unsigned loops = SMBUS_TIMEOUT;

src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c

@@ -19,9 +19,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val);
 
 #ifdef UNUSED_CODE
+int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val);
+
 static int set_ht_link_mcp55(uint8_t ht_c_num)
 {
 	unsigned vendorid = 0x10de;