baytrail: Basic DPTF framework
This is not complete yet but it compiles and doesn't cause any issues by itself. It is tied into the EC pretty closely so that is part of the same commit. Once we have more of the EC support done it will need some more work to make use of those new interfaces properly. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: I4b27e38baae18627a275488d77944208950b98bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179459 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Duncan Laurie
Kyösti Mälkki
parent
4cc4b04d8a
commit
ad8d913f42
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@ -25,6 +25,7 @@
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// Mainboard specific throttle handler
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External (\_TZ.THRT, MethodObj)
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External (\_SB.DPTF.TEVT, MethodObj)
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Device (EC0)
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{
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@ -47,6 +48,7 @@ Device (EC0)
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TSTB, 8, // Test Byte
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TSTC, 8, // Complement of Test Byte
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KBLV, 8, // Keyboard Backlight
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FAND, 8, // Set Fan Duty Cycle
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}
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OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
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@ -89,6 +91,8 @@ Device (EC0)
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BMOD, 64, // Battery Model String
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BSER, 64, // Battery Serial String
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BTYP, 64, // Battery Type String
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Offset (0x80),
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ALS0, 16, // ALS reading 0 in lux
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}
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Method (TINS, 1, Serialized)
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@ -134,6 +138,40 @@ Device (EC0)
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Store (LIDS, \LIDS)
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}
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/* Read requested temperature and check against EC error values */
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Method (TSRD, 1, Serialized)
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{
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Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0)
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/* Check for sensor not calibrated */
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
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Return (Zero)
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}
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/* Check for sensor not present */
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
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Return (Zero)
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}
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/* Check for sensor not powered */
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
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Return (Zero)
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}
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/* Check for sensor bad reading */
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
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Return (Zero)
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}
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/* Adjust by offset to get Kelvin */
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Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
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/* Convert to 1/10 Kelvin */
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Multiply (Local0, 10, Local0)
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Return (Local0)
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}
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// Lid Closed Event
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Method (_Q01, 0, NotSerialized)
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{
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@ -247,6 +285,39 @@ Device (EC0)
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}
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}
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/*
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* Dynamic Platform Thermal Framework support
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*/
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/*
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* Set Aux Trip Point 0
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* Arg0 = Temp Sensor ID
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* Arg1 = Value to set
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*/
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Method (PAT0, 2, Serialized)
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{
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}
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/*
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* Set Aux Trip Point 1
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* Arg0 = Temp Sensor ID
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* Arg1 = Value to set
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*/
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Method (PAT1, 2, Serialized)
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{
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}
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/*
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* DPTF Thermal Threshold Event
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*/
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Method (_Q14, 0, Serialized)
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{
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Store ("EC: DPTF THERMAL THRESHOLD", Debug)
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If (CondRefOf (\_SB.DPTF.TEVT, Local0)) {
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\_SB.DPTF.TEVT ()
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}
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}
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#include "ac.asl"
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#include "battery.asl"
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}
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@ -338,8 +338,8 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* Write _PCT indicating use of FFixedHW */
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len = acpigen_write_empty_PCT();
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/* Write _PPC with no limit on supported P-state */
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len += acpigen_write_PPC(0);
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/* Write _PPC with NVS specified limit on supported P-state */
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len += acpigen_write_PPC_NVS();
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/* Write PSD indicating configured coordination type */
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len += acpigen_write_PSD_package(core, 1, coord_type);
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@ -0,0 +1,36 @@
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Device (TCHG)
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{
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Name (_HID, "INT3403")
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Name (_UID, 0)
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Name (PTYP, 0x0B)
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Name (_STR, Unicode("Battery Charger"))
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Method (_STA)
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{
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If (LEqual (\DPTE, One)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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Name (PPSS, Package ()
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{
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Package () { 0, 0, 0, 0, 0, 0x880, "mA", 0 }, /* 2.1A */
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Package () { 0, 0, 0, 0, 1, 0x800, "mA", 0 }, /* 2.0A */
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Package () { 0, 0, 0, 0, 2, 0x600, "mA", 0 }, /* 1.5A */
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Package () { 0, 0, 0, 0, 3, 0x400, "mA", 0 }, /* 1.0A */
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Package () { 0, 0, 0, 0, 4, 0x200, "mA", 0 }, /* 0.5A */
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Package () { 0, 0, 0, 0, 5, 0x000, "mA", 0 }, /* 0.0A */
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})
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Method (PPPC)
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{
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Return (0)
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}
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Method (SPPC, 1, Serialized)
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{
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/* TODO: Tell EC to limit battery charging */
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}
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}
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@ -0,0 +1,180 @@
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External (\_PR.CPU0._TSS, MethodObj)
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External (\_PR.CPU0._TPC, MethodObj)
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External (\_PR.CPU0._PTC, PkgObj)
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External (\_PR.CPU0._TSD, PkgObj)
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External (\_PR.CPU0._PPC, MethodObj)
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External (\_PR.CPU0._PSS, MethodObj)
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Device (TCPU)
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{
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Name (_HID, EISAID ("INT3401"))
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Name (_UID, 0)
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Name (CTYP, 0) /* Passive Cooling by default */
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Method (_STA)
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{
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If (LEqual (\DPTE, One)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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/*
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* Processor Throttling Controls
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*/
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Method (_TSS)
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{
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If (CondRefOf (\_PR.CPU0._TSS)) {
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Return (\_PR.CPU0._TSS)
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} Else {
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Return (Package ()
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{
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Package () { 0, 0, 0, 0, 0 }
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})
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}
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}
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Method (_TPC)
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{
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If (CondRefOf (\_PR.CPU0._TPC)) {
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Return (\_PR.CPU0._TPC)
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} Else {
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Return (0)
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}
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}
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Method (_PTC)
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{
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If (CondRefOf (\_PR.CPU0._PTC)) {
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Return (\_PR.CPU0._PTC)
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} Else {
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Return (Package ()
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{
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Buffer () { 0 },
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Buffer () { 0 }
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})
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}
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}
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Method (_TSD)
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{
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If (CondRefOf (\_PR.CPU0._TSD)) {
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Return (\_PR.CPU0._TSD)
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} Else {
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Return (Package ()
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{
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Package () { 5, 0, 0, 0, 0 }
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})
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}
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}
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Method (_TDL)
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{
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If (CondRefOf (\_PR.CPU0._TSS)) {
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Store (SizeOf (\_PR.CPU0._TSS ()), Local0)
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Decrement (Local0)
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Return (Local0)
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} Else {
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Return (0)
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}
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}
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/*
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* Processor Performance Control
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*/
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Method (_PPC)
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{
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If (CondRefOf (\_PR.CPU0._PPC)) {
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Return (\_PR.CPU0._PPC)
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} Else {
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Return (0)
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}
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}
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Method (SPPC, 1)
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{
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Store (Arg0, \PPCM)
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/* Notify OS to re-read _PPC limit on each CPU */
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\PPCN ()
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}
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Method (_PSS)
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{
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If (CondRefOf (\_PR.CPU0._PSS)) {
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Return (\_PR.CPU0._PSS)
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} Else {
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Return (Package ()
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{
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Package () { 0, 0, 0, 0, 0, 0 }
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})
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}
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}
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Method (_PDL)
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{
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If (CondRefOf (\_PR.CPU0._PSS)) {
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Store (SizeOf (\_PR.CPU0._PSS ()), Local0)
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Decrement (Local0)
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Return (Local0)
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} Else {
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Return (0)
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}
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}
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/*
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* DPTF
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*/
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/* Convert from Degrees C to 1/10 Kelvin for ACPI */
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Method (CTOK, 1) {
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/* 10th of Degrees C */
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Multiply (Arg0, 10, Local0)
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/* Convert to Kelvin */
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Add (Local0, 2732, Local0)
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Return (Local0)
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}
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/* Critical temperature from NVS */
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Method (_CRT, 0, Serialized)
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{
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Return (CTOK (\TCRT))
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}
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/* Hot temperature is 3 less than critical temperature */
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Method (_HOT, 0, Serialized)
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{
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Return (CTOK (Subtract (\TCRT, 3)))
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}
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Method (_PSV, 0, Serialized)
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{
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If (CTYP) {
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Return (CTOK (\TACT))
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} Else {
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Return (CTOK (\TPSV))
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}
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}
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/* Set Cooling Policy
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* Arg0 - Cooling policy mode, 1=active, 0=passive
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* Arg1 - Acoustic Limit
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* Arg2 - Power Limit
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*/
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Method (_SCP, 3, Serialized)
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{
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If (LEqual (Arg0, 0)) {
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Store (0, CTYP)
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} Else {
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Store (1, CTYP)
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}
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/* DPTF Thermal Trip Points Changed Event */
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Notify (TCPU, 0x91)
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}
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}
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@ -0,0 +1,51 @@
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Device (DPTF)
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{
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Name (_HID, EISAID ("INT3400"))
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Name (_UID, 0)
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Name (IDSP, Package()
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{
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/* DPPM Passive Policy 1.0 */
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ToUUID("42A441D6-AE6A-462B-A84B-4A8CE79027D3"),
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/* DPPM Critical Policy */
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ToUUID("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"),
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/* DPPM Cooling Policy */
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ToUUID("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"),
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})
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Method (_STA)
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{
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If (LEqual (\DPTE, One)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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Method (_OSC, 4, Serialized)
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{
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/* TODO: Enable/Disable EC control of thermals/charging */
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Return (Arg3)
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}
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Method (_TRT)
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{
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Return (\_SB.DTRT)
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}
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/* Thermal Threshold Event Handler */
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Method (TEVT, 0, Serialized)
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{
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}
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/* Include CPU Participant */
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#include "cpu.asl"
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/* Include Thermal Participants */
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#include "thermal.asl"
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/* Include Charger Participant */
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#include "charger.asl"
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}
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@ -0,0 +1,116 @@
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#ifdef DPTF_TSR0_SENSOR_ID
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Device (TSR0)
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{
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Name (_HID, EISAID ("INT3403"))
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Name (_UID, 1)
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Name (PTYP, 0x03)
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Name (TMPI, DPTF_TSR0_SENSOR_ID)
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Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME))
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Method (_STA)
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{
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If (LEqual (\DPTE, One)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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Method (_TMP, 0, Serialized)
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{
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Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
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}
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Name (PATC, 2)
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/* Set Aux Trip Point */
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Method (PAT0, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
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}
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/* Set Aux Trip Point */
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Method (PAT1, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
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}
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}
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#endif
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#ifdef DPTF_TSR1_SENSOR_ID
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Device (TSR1)
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{
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Name (_HID, EISAID ("INT3403"))
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Name (_UID, 2)
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Name (PTYP, 0x03)
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Name (TMPI, DPTF_TSR1_SENSOR_ID)
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Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME))
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Method (_STA)
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{
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If (LEqual (\DPTE, One)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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Method (_TMP, 0, Serialized)
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{
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Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
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}
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Name (PATC, 2)
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/* Set Aux Trip Point */
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Method (PAT0, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
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}
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/* Set Aux Trip Point */
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Method (PAT1, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
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}
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}
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#endif
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#ifdef DPTF_TSR2_SENSOR_ID
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Device (TSR2)
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{
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Name (_HID, EISAID ("INT3403"))
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Name (_UID, 3)
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Name (PTYP, 0x03)
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Name (TMPI, DPTF_TSR2_SENSOR_ID)
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Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME))
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Method (_STA)
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{
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If (LEqual (\DPTE, One)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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Method (_TMP, 0, Serialized)
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{
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Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
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}
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Name (PATC, 2)
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/* Set Aux Trip Point */
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Method (PAT0, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
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}
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/* Set Aux Trip Point */
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Method (PAT1, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
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}
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}
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#endif
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@ -51,6 +51,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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PCNT, 8, // 0x11 - Processor count
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TPMP, 8, // 0x12 - TPM Present and Enabled
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TLVL, 8, // 0x13 - Throttle Level
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PPCM, 8, // 0x14 - Maximum P-state usable by OS
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/* Device Config */
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Offset (0x20),
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@ -58,6 +59,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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S5U1, 8, // 0x21 - Enable USB1 in S5
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S3U0, 8, // 0x22 - Enable USB0 in S3
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S3U1, 8, // 0x23 - Enable USB1 in S3
|
||||
TACT, 8, // 0x24 - Thermal Active trip point
|
||||
TPSV, 8, // 0x25 - Thermal Passive trip point
|
||||
TCRT, 8, // 0x26 - Thermal Critical trip point
|
||||
DPTE, 8, // 0x27 - Enable DPTF
|
||||
|
||||
/* Base addresses */
|
||||
Offset (0x30),
|
||||
|
|
|
|||
|
|
@ -37,14 +37,19 @@ typedef struct {
|
|||
u8 pcnt; /* 0x11 - Processor Count */
|
||||
u8 tpmp; /* 0x12 - TPM Present and Enabled */
|
||||
u8 tlvl; /* 0x13 - Throttle Level */
|
||||
u8 rsvd1[12];
|
||||
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
|
||||
u8 rsvd1[11];
|
||||
|
||||
/* Device Config */
|
||||
u8 s5u0; /* 0x20 - Enable USB0 in S5 */
|
||||
u8 s5u1; /* 0x21 - Enable USB1 in S5 */
|
||||
u8 s3u0; /* 0x22 - Enable USB0 in S3 */
|
||||
u8 s3u1; /* 0x23 - Enable USB1 in S3 */
|
||||
u8 rsvd2[12];
|
||||
u8 tact; /* 0x24 - Thermal Active trip point */
|
||||
u8 tpsv; /* 0x25 - Thermal Passive trip point */
|
||||
u8 tcrt; /* 0x26 - Thermal Critical trip point */
|
||||
u8 dpte; /* 0x27 - Enable DPTF */
|
||||
u8 rsvd2[8];
|
||||
|
||||
/* Base Addresses */
|
||||
u32 cmem; /* 0x30 - CBMEM TOC */
|
||||
|
|
|
|||
Loading…
Reference in New Issue