intel/skylake: Use new PCIe RP devicetree update
The old code stumbled when the whole first group of root ports was disabled and also made the (sometimes wrong) assumption that FSP would only hide function 0 if we explicitly told it to disable it. Change-Id: Ia6938ca6929c6d9d0293c4f0f0421e38bf53fb55 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36702 Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Nico Huber
parent
5e8afce88f
commit
ad91b18c64
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@ -15,10 +15,8 @@
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#include <bootmode.h>
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#include <bootstate.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <arch/acpi.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_ids.h>
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@ -27,6 +25,7 @@
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/pcie_rp.h>
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#include <intelblocks/xdci.h>
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#include <intelblocks/p2sb.h>
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#include <intelpch/lockdown.h>
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@ -44,129 +43,22 @@
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#include "chip.h"
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struct pcie_entry {
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unsigned int devfn;
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unsigned int func_count;
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static const struct pcie_rp_group pch_lp_rp_groups[] = {
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{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
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{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
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{ 0 }
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};
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/*
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* According to table 2-2 in doc#546717:
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* PCI bus[function] ID
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* D28:[F0 - F7] 0xA110 - 0xA117
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* D29:[F0 - F7] 0xA118 - 0xA11F
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* D27:[F0 - F3] 0xA167 - 0xA16A
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*/
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static const struct pcie_entry pcie_table_skl_pch_h[] = {
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{PCH_DEVFN_PCIE1, 8},
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{PCH_DEVFN_PCIE9, 8},
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{PCH_DEVFN_PCIE17, 4},
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static const struct pcie_rp_group pch_h_rp_groups[] = {
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{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
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{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
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/* Sunrise Point PCH-H actually only has 4 ports in the
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third group. But that would require a runtime check
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and probing 4 non-existent ports shouldn't hurt. */
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{ .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
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{ 0 }
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};
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/*
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* According to table 2-2 in doc#564464:
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* PCI bus[function] ID
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* D28:[F0 - F7] 0xA290 - 0xA297
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* D29:[F0 - F7] 0xA298 - 0xA29F
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* D27:[F0 - F7] 0xA2E7 - 0xA2EE
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*/
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static const struct pcie_entry pcie_table_kbl_pch_h[] = {
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{PCH_DEVFN_PCIE1, 8},
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{PCH_DEVFN_PCIE9, 8},
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{PCH_DEVFN_PCIE17, 8},
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};
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/*
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* According to table 2-2 in doc#567995/545659:
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* PCI bus[function] ID
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* D28:[F0 - F7] 0x9D10 - 0x9D17
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* D29:[F0 - F3] 0x9D18 - 0x9D1B
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*/
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static const struct pcie_entry pcie_table_skl_pch_lp[] = {
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{PCH_DEVFN_PCIE1, 8},
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{PCH_DEVFN_PCIE9, 4},
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};
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/*
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* If the PCIe root port at function 0 is disabled,
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* the PCIe root ports might be coalesced after FSP silicon init.
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* The below function will swap the devfn of the first enabled device
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* in devicetree and function 0 resides a pci device
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* so that it won't confuse coreboot.
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*/
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static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group,
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size_t pci_groups)
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{
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struct device *func0;
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unsigned int devfn, devfn0;
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int i, group;
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unsigned int inc = PCI_DEVFN(0, 1);
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for (group = 0; group < pci_groups; group++) {
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devfn0 = pcie_rp_group[group].devfn;
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func0 = pcidev_path_on_root(devfn0);
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if (func0 == NULL)
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continue;
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/* No more functions if function 0 is disabled. */
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if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff)
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continue;
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devfn = devfn0 + inc;
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/*
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* Increase function by 1.
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* Then find first enabled device to replace func0
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* as that port was move to func0.
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*/
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for (i = 1; i < pcie_rp_group[group].func_count;
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i++, devfn += inc) {
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struct device *dev = pcidev_path_on_root(devfn);
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if (dev == NULL || !dev->enabled)
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continue;
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/*
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* Found the first enabled device in
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* a given dev number.
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*/
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printk(BIOS_INFO, "PCI func %d was swapped"
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" to func 0.\n", i);
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func0->path.pci.devfn = dev->path.pci.devfn;
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dev->path.pci.devfn = devfn0;
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break;
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}
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}
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}
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static void pcie_override_devicetree_after_silicon_init(void)
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{
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uint16_t id, id_mask;
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id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID);
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/*
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* We may read an ID other than func 0 after FSP-S.
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* Strip out 4 least significant bits.
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*/
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id_mask = id & ~0xf;
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printk(BIOS_INFO, "Override DT after FSP-S, PCH is ");
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if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) {
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printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n");
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pcie_update_device_tree(&pcie_table_skl_pch_lp[0],
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ARRAY_SIZE(pcie_table_skl_pch_lp));
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} else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) {
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printk(BIOS_INFO, "KBL PCH-H SKU\n");
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pcie_update_device_tree(&pcie_table_kbl_pch_h[0],
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ARRAY_SIZE(pcie_table_kbl_pch_h));
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} else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) {
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printk(BIOS_INFO, "SKL PCH-H SKU\n");
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pcie_update_device_tree(&pcie_table_skl_pch_h[0],
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ARRAY_SIZE(pcie_table_skl_pch_h));
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} else {
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printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x"
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" is not found\n", id);
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return;
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}
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}
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void soc_init_pre_device(void *chip_info)
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{
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/* Snapshot the current GPIO IRQ polarities. FSP is setting a
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@ -187,7 +79,10 @@ void soc_init_pre_device(void *chip_info)
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itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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/* swap enabled PCI ports in device tree if needed */
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pcie_override_devicetree_after_silicon_init();
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if (CONFIG(SKYLAKE_SOC_PCH_H))
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pcie_rp_update_devicetree(pch_h_rp_groups);
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else
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pcie_rp_update_devicetree(pch_lp_rp_groups);
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}
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void soc_fsp_load(void)
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