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mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms 

Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):

- mrc_cache_load_current: fetches the mrc_cache data and drops it into
  the given buffer.  This is useful for ARM platforms where the mmap
  operation is very expensive.

- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
  given buffer.  This is useful for platforms where the mmap operation
  is a no-op (like x86 platforms).  As the name mentions, we are not
  freeing the memory that we allocated with the mmap, so it is the
  caller's responsibility to do so.

Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot.  This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).

BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
     reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2020-07-23 16:10:52 -07:00
parent 73f8986ad2
commit ad9cd687b8
13 changed files with 198 additions and 127 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/drivers/intel/fsp1_1/romstage.c
View File

@ -23,7 +23,7 @@
static void raminit_common(struct romstage_params *params)
{
bool s3wake;
struct region_device rdev;
size_t mrc_size;
post_code(0x32);
@ -45,24 +45,31 @@ static void raminit_common(struct romstage_params *params)
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG,
"Recovery mode: not using MRC cache.\n");
} else if (CONFIG(CACHE_MRC_SETTINGS)
&& (!mrc_cache_get_current(MRC_TRAINING_DATA,
params->fsp_version,
&rdev))) {
/* MRC cache found */
params->saved_data_size = region_device_sz(&rdev);
params->saved_data = rdev_mmap_full(&rdev);
} else {
/* Assume boot device is memory mapped. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
} else if (s3wake) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
/* FIXME: A "system" reset is likely enough: */
full_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
params->saved_data = NULL;
if (CONFIG(CACHE_MRC_SETTINGS))
params->saved_data =
mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
params->fsp_version,
&mrc_size);
if (params->saved_data) {
/* MRC cache found */
params->saved_data_size = mrc_size;
} else if (s3wake) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache "
"found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
/* FIXME: A "system" reset is likely enough: */
full_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
}
}
}
@ -283,13 +290,6 @@ __weak void mainboard_add_dimm_info(
{
}
/* Get the memory configuration data */
__weak int mrc_cache_get_current(int type, uint32_t version,
struct region_device *rdev)
{
return -1;
}
/* Save the memory configuration data */
__weak int mrc_cache_stash_data(int type, uint32_t version,
const void *data, size_t size)

13
src/drivers/intel/fsp2_0/memory_init.c
View File

@ -93,8 +93,8 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
{
struct region_device rdev;
void *data;
size_t mrc_size;
arch_upd->NvsBufferPtr = NULL;
@ -113,25 +113,22 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
return;
}
if (mrc_cache_get_current(MRC_TRAINING_DATA, fsp_version, &rdev) < 0)
return;
/* Assume boot device is memory mapped. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
data = rdev_mmap_full(&rdev);
data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, fsp_version,
&mrc_size);
if (data == NULL)
return;
if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) &&
!mrc_cache_verify_hash(data, region_device_sz(&rdev)))
!mrc_cache_verify_hash(data, mrc_size))
return;
/* MRC cache found */
arch_upd->NvsBufferPtr = data;
printk(BIOS_SPEW, "MRC cache found, size %zx\n",
region_device_sz(&rdev));
printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size);
}
static enum cb_err check_region_overlap(const struct memranges *ranges,

106
src/drivers/mrc_cache/mrc_cache.c
View File

@ -204,23 +204,16 @@ static int mrc_header_valid(struct region_device *rdev, struct mrc_metadata *md)
return 0;
}
static int mrc_data_valid(const struct region_device *rdev,
const struct mrc_metadata *md)
static int mrc_data_valid(const struct mrc_metadata *md,
void *data, size_t data_size)
{
void *data;
uint16_t checksum;
const size_t md_size = sizeof(*md);
const size_t data_size = md->data_size;
data = rdev_mmap(rdev, md_size, data_size);
if (data == NULL) {
printk(BIOS_ERR, "MRC: mmap failure on data verification.\n");
if (md->data_size != data_size)
return -1;
}
checksum = compute_ip_checksum(data, data_size);
rdev_munmap(rdev, data);
if (md->data_checksum != checksum) {
printk(BIOS_ERR, "MRC: data checksum mismatch: %x vs %x\n",
md->data_checksum, checksum);
@ -230,7 +223,7 @@ static int mrc_data_valid(const struct region_device *rdev,
return 0;
}
static int mrc_cache_latest(const char *name,
static int mrc_cache_get_latest_slot_info(const char *name,
const struct region_device *backing_rdev,
struct mrc_metadata *md,
struct region_file *cache_file,
@ -260,25 +253,19 @@ static int mrc_cache_latest(const char *name,
return fail_bad_data ? -1 : 0;
}
/* Validate Data */
if (mrc_data_valid(rdev, md) < 0) {
printk(BIOS_ERR, "MRC: invalid data in '%s'\n", name);
return fail_bad_data ? -1 : 0;
}
return 0;
}
int mrc_cache_get_current(int type, uint32_t version,
struct region_device *rdev)
static int mrc_cache_find_current(int type, uint32_t version,
struct region_device *rdev,
struct mrc_metadata *md)
{
const struct cache_region *cr;
struct region region;
struct region_device read_rdev;
struct region_file cache_file;
struct mrc_metadata md;
size_t data_size;
const size_t md_size = sizeof(md);
const size_t md_size = sizeof(*md);
const bool fail_bad_data = true;
cr = lookup_region(&region, type);
@ -289,21 +276,75 @@ int mrc_cache_get_current(int type, uint32_t version,
if (boot_device_ro_subregion(&region, &read_rdev) < 0)
return -1;
if (mrc_cache_latest(cr->name, &read_rdev, &md, &cache_file, rdev,
fail_bad_data) < 0)
if (mrc_cache_get_latest_slot_info(cr->name,
&read_rdev,
md,
&cache_file,
rdev,
fail_bad_data) < 0)
return -1;
if (version != md.version) {
if (version != md->version) {
printk(BIOS_INFO, "MRC: version mismatch: %x vs %x\n",
md.version, version);
md->version, version);
return -1;
}
/* Re-size rdev to only contain the data. i.e. remove metadata. */
data_size = md.data_size;
data_size = md->data_size;
return rdev_chain(rdev, rdev, md_size, data_size);
}
int mrc_cache_load_current(int type, uint32_t version, void *buffer,
size_t buffer_size)
{
struct region_device rdev;
struct mrc_metadata md;
size_t data_size;
if (mrc_cache_find_current(type, version, &rdev, &md) < 0)
return -1;
data_size = region_device_sz(&rdev);
if (buffer_size < data_size)
return -1;
if (rdev_readat(&rdev, buffer, 0, data_size) != data_size)
return -1;
if (mrc_data_valid(&md, buffer, data_size) < 0)
return -1;
return 0;
}
void *mrc_cache_current_mmap_leak(int type, uint32_t version,
size_t *data_size)
{
struct region_device rdev;
void *data;
size_t region_device_size;
struct mrc_metadata md;
if (mrc_cache_find_current(type, version, &rdev, &md) < 0)
return NULL;
region_device_size = region_device_sz(&rdev);
if (data_size)
*data_size = region_device_size;
data = rdev_mmap_full(&rdev);
if (data == NULL) {
printk(BIOS_INFO, "MRC: mmap failure.\n");
return NULL;
}
if (mrc_data_valid(&md, data, region_device_size) < 0)
return NULL;
return data;
}
static bool mrc_cache_needs_update(const struct region_device *rdev,
const struct cbmem_entry *to_be_updated)
{
@ -392,8 +433,17 @@ static void update_mrc_cache_by_type(int type)
if (backing_rdev == NULL)
return;
if (mrc_cache_latest(cr->name, backing_rdev, &md, &cache_file,
&latest_rdev, fail_bad_data) < 0)
/* Note that mrc_cache_get_latest_slot_info doesn't check the
* validity of the current slot. If the slot is invalid,
* we'll overwrite it anyway when we update the mrc_cache.
*/
if (mrc_cache_get_latest_slot_info(cr->name,
backing_rdev,
&md,
&cache_file,
&latest_rdev,
fail_bad_data) < 0)
return;
if (!mrc_cache_needs_update(&latest_rdev, to_be_updated)) {

29
src/include/mrc_cache.h
View File

@ -21,11 +21,30 @@ enum {
* policy don't request the data.
*/
/* Get and stash data for saving provided the type passed in. The functions
* return < 0 on error, 0 on success. */
int mrc_cache_get_current(int type, uint32_t version,
struct region_device *rdev);
/* Get and stash data for saving provided the type passed in. */
/**
* mrc_cache_load_current
*
* Fill in the buffer with the latest slot data. This will be a
* common entry point for ARM platforms. Returns < 0 on error, 0 on
* success.
*/
int mrc_cache_load_current(int type, uint32_t version, void *buffer,
size_t buffer_size);
/**
* mrc_cache_mmap_leak
*
* Return a pointer to a buffer with the latest slot data. An mmap
* will be executed (without a matching unmap). This will be a common
* entry point for platforms where mmap is considered a noop, like x86
*/
void *mrc_cache_current_mmap_leak(int type, uint32_t version,
size_t *data_size);
/**
* Returns < 0 on error, 0 on success.
*/
int mrc_cache_stash_data(int type, uint32_t version, const void *data,
size_t size);
size_t size);
#endif /* _COMMON_MRC_CACHE_H_ */

15
src/northbridge/intel/haswell/raminit.c
View File

@ -31,21 +31,24 @@ void save_mrc_data(struct pei_data *pei_data)
static void prepare_mrc_cache(struct pei_data *pei_data)
{
struct region_device rdev;
size_t mrc_size;
/* Preset just in case there is an error */
pei_data->mrc_input = NULL;
pei_data->mrc_input_len = 0;
if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev))
pei_data->mrc_input =
mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
MRC_CACHE_VERSION,
&mrc_size);
if (!pei_data->mrc_input)
/* Error message printed in find_current_mrc_cache */
return;
pei_data->mrc_input = rdev_mmap_full(&rdev);
pei_data->mrc_input_len = region_device_sz(&rdev);
pei_data->mrc_input_len = mrc_size;
printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input,
pei_data->mrc_input_len);
printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__,
pei_data->mrc_input, mrc_size);
}
static const char *ecc_decoder[] = {

8
src/northbridge/intel/ironlake/raminit.c
View File

@ -1618,11 +1618,9 @@ static void save_timings(struct raminfo *info)
static const struct ram_training *get_cached_training(void)
{
struct region_device rdev;
if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
&rdev))
return 0;
return (void *)rdev_mmap_full(&rdev);
return mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
MRC_CACHE_VERSION,
NULL);
}
/* FIXME: add timeout. */

11
src/northbridge/intel/sandybridge/raminit.c
View File

@ -297,7 +297,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
int me_uma_size, cbmem_was_inited, fast_boot, err;
ramctr_timing ctrl;
spd_raw_data spds[4];
struct region_device rdev;
size_t mrc_size;
ramctr_timing *ctrl_cached = NULL;
MCHBAR32(SAPMCTL) |= 1;
@ -324,10 +324,11 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
early_thermal_init();
/* Try to find timings in MRC cache */
err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev);
if (!err && !(region_device_sz(&rdev) < sizeof(ctrl)))
ctrl_cached = rdev_mmap_full(&rdev);
ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
MRC_CACHE_VERSION,
&mrc_size);
if (mrc_size < sizeof(ctrl))
ctrl_cached = NULL;
/* Before reusing training data, assert that the CPU has not been replaced */
if (ctrl_cached && cpuid != ctrl_cached->cpu) {

14
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -72,8 +72,8 @@ void save_mrc_data(struct pei_data *pei_data)
static void prepare_mrc_cache(struct pei_data *pei_data)
{
struct region_device rdev;
u16 c1, c2, checksum, seed_checksum;
size_t mrc_size;
/* Preset just in case there is an error */
pei_data->mrc_input = NULL;
@ -103,16 +103,18 @@ static void prepare_mrc_cache(struct pei_data *pei_data)
return;
}
if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) {
pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
MRC_CACHE_VERSION,
&mrc_size);
if (pei_data->mrc_input == NULL) {
/* Error message printed in find_current_mrc_cache */
return;
}
pei_data->mrc_input = rdev_mmap_full(&rdev);
pei_data->mrc_input_len = region_device_sz(&rdev);
pei_data->mrc_input_len = mrc_size;
printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input,
pei_data->mrc_input_len);
printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__,
pei_data->mrc_input, mrc_size);
}
/**

14
src/northbridge/intel/x4x/raminit.c
View File

@ -610,8 +610,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
{
struct sysinfo s, *ctrl_cached;
u8 reg8;
int fast_boot, cbmem_was_inited, cache_not_found;
struct region_device rdev;
int fast_boot, cbmem_was_inited;
size_t mrc_size;
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
@ -620,10 +620,11 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
memset(&s, 0, sizeof(struct sysinfo));
cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA,
MRC_CACHE_VERSION, &rdev);
ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
MRC_CACHE_VERSION,
&mrc_size);
if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) {
if (!ctrl_cached || mrc_size < sizeof(s)) {
if (boot_path == BOOT_PATH_RESUME) {
/* Failed S3 resume, reset to come up cleanly */
system_reset();
@ -632,9 +633,6 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
and therefore requiring valid cached settings */
full_reset();
}
ctrl_cached = NULL;
} else {
ctrl_cached = rdev_mmap_full(&rdev);
}
/* verify MRC cache for fast boot */

10
src/soc/amd/common/block/s3/s3_resume.c
View File

@ -25,14 +25,10 @@ AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock)
size_t size;
int i;
uint32_t erased = 0xffffffff;
struct region_device rdev;
if (mrc_cache_get_current(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION,
&rdev))
reboot_from_resume("mrc_cache_get_current error, rebooting.\n");
base = rdev_mmap_full(&rdev);
size = region_device_sz(&rdev);
base = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
DEFAULT_MRC_VERSION,
&size);
if (!base || !size)
reboot_from_resume("Error: S3 NV data not found, rebooting.\n");

12
src/soc/intel/apollolake/romstage.c
View File

@ -267,8 +267,6 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
struct region_device rdev;
check_full_retrain(mupd);
fill_console_params(mupd);
@ -310,11 +308,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
* wrong/missing key renders DRAM contents useless.
*/
if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) {
/* Assume leaking is ok. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev);
}
mupd->FspmConfig.VariableNvsBufferPtr =
mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version,
NULL);
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
fsp_version = version;

15
src/soc/intel/baytrail/romstage/raminit.c
View File

@ -122,8 +122,8 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
{
int ret;
mrc_wrapper_entry_t mrc_entry;
struct region_device rdev;
size_t i;
size_t mrc_size;
/* Fill in default entries. */
mp->version = MRC_PARAMS_VER;
@ -135,11 +135,14 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
if (!mp->io_hole_mb)
mp->io_hole_mb = 2048;
if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) {
mp->saved_data_size = region_device_sz(&rdev);
mp->saved_data = rdev_mmap_full(&rdev);
/* Assume boot device is memory mapped. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
/* Assume boot device is memory mapped. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
mp->saved_data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
0,
&mrc_size);
if (mp->saved_data) {
mp->saved_data_size = mrc_size;
} else if (prev_sleep_state == ACPI_S3) {
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");

30
src/soc/intel/broadwell/romstage/raminit.c
View File

@ -26,7 +26,7 @@
*/
void raminit(struct pei_data *pei_data)
{
struct region_device rdev;
size_t mrc_size;
struct memory_info *mem_info;
pei_wrapper_entry_t entry;
int ret;
@ -39,19 +39,25 @@ void raminit(struct pei_data *pei_data)
vboot_recovery_mode_enabled()) {
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
} else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) {
/* MRC cache found */
pei_data->saved_data_size = region_device_sz(&rdev);
pei_data->saved_data = rdev_mmap_full(&rdev);
} else {
/* Assume boot device is memory mapped. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
} else if (pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
pei_data->saved_data =
mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
&mrc_size);
if (pei_data->saved_data) {
/* MRC cache found */
pei_data->saved_data_size = mrc_size;
} else if (pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
}
}
/*