libpayload arm64: Add support for mmu
Adds support for initializing mmu, setting up dma areas and enabling mmu based on the memranges passed on in the coreboot tables. CQ-DEPEND=CL:216826 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: Id41a4255f1cd45a9455840f1eaa53503bd6fef3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2c6676bf51fcd85b61e9e08a261634a78137c4c Original-Change-Id: I217bc5a5aff6a1fc0809c769822d820316d5c434 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216823 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh
Patrick Georgi
parent
cc51256c74
commit
adabbe5e20
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@ -40,6 +40,7 @@ libc-y += memcpy.S memset.S memmove.S
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libc-y += exception_asm.S exception.c
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libc-y += cache.c cpu.S
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libc-y += selfboot.c
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libc-y += mmu.c
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libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c
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libgdb-y += gdb.c
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@ -117,30 +117,6 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
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dcache_op_va(addr, len, OP_DCIVAC);
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}
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/*
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* CAUTION: This implementation assumes that coreboot never uses non-identity
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* page tables for pages containing executed code. If you ever want to violate
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* this assumption, have fun figuring out the associated problems on your own.
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*/
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void dcache_mmu_disable(void)
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{
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uint32_t sctlr;
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dcache_clean_invalidate_all();
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sctlr = raw_read_sctlr_current();
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sctlr &= ~(SCTLR_C | SCTLR_M);
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raw_write_sctlr_current(sctlr);
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}
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void dcache_mmu_enable(void)
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{
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uint32_t sctlr;
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sctlr = raw_read_sctlr_current();
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sctlr |= SCTLR_C | SCTLR_M;
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raw_write_sctlr_current(sctlr);
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}
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void cache_sync_instructions(void)
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{
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dcache_clean_all(); /* includes trailing DSB (in assembly) */
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@ -0,0 +1,618 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <arch/mmu.h>
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#include <arch/lib_helpers.h>
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#include <arch/cache.h>
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/* Maximum number of XLAT Tables available based on ttb buffer size */
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static unsigned int max_tables;
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/* Address of ttb buffer */
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static uint64_t *xlat_addr;
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static int free_idx;
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static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE)));
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/*
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* The usedmem_ranges is used to describe all the memory ranges that are
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* actually used by payload i.e. _start -> _end in linker script and the
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* coreboot tables. This is required for two purposes:
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* 1) During the pre_sysinfo_scan_mmu_setup, these are the only ranges
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* initialized in the page table as we do not know the entire memory map.
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* 2) During the post_sysinfo_scan_mmu_setup, these ranges are used to check if
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* the DMA buffer is being placed in a sane location and does not overlap any of
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* the used mem ranges.
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*/
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struct mmu_ranges usedmem_ranges;
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static const uint64_t level_to_addr_mask[] = {
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L1_ADDR_MASK,
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L2_ADDR_MASK,
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L3_ADDR_MASK,
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};
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static const uint64_t level_to_addr_shift[] = {
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L1_ADDR_SHIFT,
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L2_ADDR_SHIFT,
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L3_ADDR_SHIFT,
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};
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static void __attribute__((noreturn)) mmu_error(void)
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{
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halt();
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}
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/*
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* Func : get_block_attr
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* Desc : Get block descriptor attributes based on the value of tag in memrange
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* region
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*/
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static uint64_t get_block_attr(unsigned long tag)
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{
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uint64_t attr;
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/* We should be in EL2(which is non-secure only) or EL1(non-secure) */
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attr = BLOCK_NS;
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/* Assuming whole memory is read-write */
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attr |= BLOCK_AP_RW;
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attr |= BLOCK_ACCESS;
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switch (tag) {
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case TYPE_NORMAL_MEM:
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attr |= (BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT);
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break;
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case TYPE_DEV_MEM:
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attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
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break;
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case TYPE_DMA_MEM:
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attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT;
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break;
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}
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return attr;
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}
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/*
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* Func : get_index_from_addr
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* Desc : Get index into table at a given level using appropriate bits from the
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* base address
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*/
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static uint64_t get_index_from_addr(uint64_t addr, uint8_t level)
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{
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uint64_t mask = level_to_addr_mask[level-1];
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uint8_t shift = level_to_addr_shift[level-1];
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return ((addr & mask) >> shift);
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}
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/*
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* Func : table_desc_valid
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* Desc : Check if a table entry contains valid desc
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*/
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static uint64_t table_desc_valid(uint64_t desc)
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{
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return((desc & TABLE_DESC) == TABLE_DESC);
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}
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/*
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* Func : get_new_table
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* Desc : Return the next free XLAT table from ttb buffer
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*/
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static uint64_t *get_new_table(void)
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{
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uint64_t *new;
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if (free_idx >= max_tables) {
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printf("ARM64 MMU: No free table\n");
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return NULL;
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}
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new = (uint64_t*)((unsigned char *)xlat_addr + free_idx * GRANULE_SIZE);
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free_idx++;
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memset(new, 0, GRANULE_SIZE);
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return new;
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}
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/*
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* Func : get_table_from_desc
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* Desc : Get next level table address from table descriptor
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*/
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static uint64_t *get_table_from_desc(uint64_t desc)
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{
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uint64_t *ptr = (uint64_t*)(desc & XLAT_TABLE_MASK);
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return ptr;
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}
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/*
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* Func: get_next_level_table
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* Desc: Check if the table entry is a valid descriptor. If not, allocate new
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* table, update the entry and return the table addr. If valid, return the addr.
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*/
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static uint64_t *get_next_level_table(uint64_t *ptr)
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{
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uint64_t desc = *ptr;
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if (!table_desc_valid(desc)) {
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uint64_t *new_table = get_new_table();
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if (new_table == NULL)
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return NULL;
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desc = ((uint64_t)new_table) | TABLE_DESC;
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*ptr = desc;
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}
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return get_table_from_desc(desc);
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}
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/*
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* Func : init_xlat_table
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* Desc : Given a base address and size, it identifies the indices within
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* different level XLAT tables which map the given base addr. Similar to table
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* walk, except that all invalid entries during the walk are updated
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* accordingly. On success, it returns the size of the block/page addressed by
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* the final table.
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*/
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static uint64_t init_xlat_table(uint64_t base_addr,
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uint64_t size,
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uint64_t tag)
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{
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uint64_t l1_index = get_index_from_addr(base_addr,1);
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uint64_t l2_index = get_index_from_addr(base_addr,2);
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uint64_t l3_index = get_index_from_addr(base_addr,3);
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uint64_t *table = xlat_addr;
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uint64_t desc;
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uint64_t attr = get_block_attr(tag);
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/*
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* L1 table lookup
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* If VA has bits more than 41, lookup starts at L1
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*/
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if (l1_index) {
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table = get_next_level_table(&table[l1_index]);
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if (!table)
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return 0;
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}
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/*
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* L2 table lookup
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* If lookup was performed at L1, L2 table addr is obtained from L1 desc
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* else, lookup starts at ttbr address
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*/
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if (!l3_index && (size >= L2_XLAT_SIZE)) {
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/*
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* If block address is aligned and size is greater than or equal
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* to 512MiB i.e. size addressed by each L2 entry, we can
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* directly store a block desc
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*/
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desc = base_addr | BLOCK_DESC | attr;
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table[l2_index] = desc;
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/* L3 lookup is not required */
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return L2_XLAT_SIZE;
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} else {
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/* L2 entry stores a table descriptor */
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table = get_next_level_table(&table[l2_index]);
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if (!table)
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return 0;
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}
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/* L3 table lookup */
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desc = base_addr | PAGE_DESC | attr;
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table[l3_index] = desc;
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return L3_XLAT_SIZE;
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}
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/*
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* Func : sanity_check
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* Desc : Check if the address is aligned and size is atleast the granule size
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*/
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static uint64_t sanity_check(uint64_t addr,
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uint64_t size)
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{
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/* Address should be atleast 64 KiB aligned */
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if (addr & GRANULE_SIZE_MASK)
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return 1;
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/* Size should be atleast granule size */
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if (size < GRANULE_SIZE)
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return 1;
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return 0;
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}
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/*
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* Func : init_mmap_entry
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* Desc : For each mmap entry, this function calls init_xlat_table with the base
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* address. Based on size returned from init_xlat_table, base_addr is updated
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* and subsequent calls are made for initializing the xlat table until the whole
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* region is initialized.
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*/
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static void init_mmap_entry(struct mmu_memrange *r)
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{
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uint64_t base_addr = r->base;
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uint64_t size = r->size;
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uint64_t tag = r->type;
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uint64_t temp_size = size;
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while (temp_size) {
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uint64_t ret;
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if (sanity_check(base_addr,temp_size)) {
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printf("Libpayload: ARM64 MMU: sanity check failed\n");
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return;
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}
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ret = init_xlat_table(base_addr + (size - temp_size),
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temp_size, tag);
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if (ret == 0)
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return;
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temp_size -= ret;
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}
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}
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/*
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* Func : mmu_init
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* Desc : Initialize mmu based on the mmu_memrange passed. ttb_buffer is used as
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* the base address for xlat tables. TTB_DEFAULT_SIZE defines the max number of
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* tables that can be used
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* Assuming that memory 0-2GiB is device memory.
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*/
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uint64_t mmu_init(struct mmu_ranges *mmu_ranges)
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{
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struct mmu_memrange devrange = { 0, 0x80000000, TYPE_DEV_MEM };
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int i = 0;
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xlat_addr = (uint64_t *)&ttb_buffer;
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memset((void*)xlat_addr, 0, GRANULE_SIZE);
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max_tables = (TTB_DEFAULT_SIZE >> GRANULE_SIZE_SHIFT);
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free_idx = 1;
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printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n",
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(void*)xlat_addr, max_tables);
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init_mmap_entry(&devrange);
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for (; i < mmu_ranges->used; i++) {
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init_mmap_entry(&mmu_ranges->entries[i]);
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}
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printf("Libpayload ARM64: MMU init done\n");
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return 0;
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}
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static uint32_t is_mmu_enabled(void)
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{
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uint32_t sctlr;
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sctlr = raw_read_sctlr_current();
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return (sctlr & SCTLR_M);
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}
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/*
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* Func: mmu_disable
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* Desc: Invalidate caches and disable mmu
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*/
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void mmu_disable(void)
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{
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uint32_t sctlr;
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sctlr = raw_read_sctlr_current();
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sctlr &= ~(SCTLR_C | SCTLR_M | SCTLR_I);
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tlbiall_current();
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dcache_clean_invalidate_all();
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dsb();
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isb();
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raw_write_sctlr_current(sctlr);
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dcache_clean_invalidate_all();
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dsb();
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isb();
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}
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/*
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* Func: mmu_enable
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* Desc: Initialize MAIR, TCR, TTBR and enable MMU by setting appropriate bits
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* in SCTLR
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*/
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void mmu_enable(void)
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{
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uint32_t sctlr;
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/* Initialize MAIR indices */
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raw_write_mair_current(MAIR_ATTRIBUTES);
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/* Invalidate TLBs */
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tlbiall_current();
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/* Initialize TCR flags */
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raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |
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TCR_SH0_IS | TCR_TG0_64KB | TCR_PS_64GB |
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TCR_TBI_USED);
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/* Initialize TTBR */
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raw_write_ttbr0_current((uintptr_t)xlat_addr);
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/* Ensure all translation table writes are committed before enabling MMU */
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dsb();
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isb();
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/* Enable MMU */
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sctlr = raw_read_sctlr_current();
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sctlr |= SCTLR_C | SCTLR_M | SCTLR_I;
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raw_write_sctlr_current(sctlr);
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isb();
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if(is_mmu_enabled())
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printf("ARM64: MMU enable done\n");
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else
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printf("ARM64: MMU enable failed\n");
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}
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/*
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* Func: mmu_is_dma_range_valid
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* Desc: We need to ensure that the dma buffer being allocated doesnt overlap
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* with any used memory range. Basically:
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* 1. Memory ranges used by the payload (usedmem_ranges)
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* 2. Any area that falls below _end symbol in linker script (Kernel needs to be
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* loaded in lower areas of memory, So, the payload linker script can have
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* kernel memory below _start and _end. Thus, we want to make sure we do not
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* step in those areas as well.
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* Returns: 1 on success, 0 on error
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* ASSUMPTION: All the memory used by payload resides below the program
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* proper. If there is any memory used above the _end symbol, then it should be
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* marked as used memory in usedmem_ranges during the presysinfo_scan.
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*/
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static int mmu_is_dma_range_valid(uint64_t dma_base,
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uint64_t dma_end)
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{
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uint64_t payload_end = (uint64_t)&_end;
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uint64_t i = 0;
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struct mmu_memrange *r = &usedmem_ranges.entries[0];
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if ((dma_base <= payload_end) || (dma_end <= payload_end))
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return 0;
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for (; i < usedmem_ranges.used; i++) {
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uint64_t start = r[i].base;
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uint64_t end = start + r[i].size;
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if (((dma_base >= start) && (dma_base <= end)) ||
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((dma_end >= start) && (dma_end <= end)))
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return 0;
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}
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return 1;
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}
|
||||
|
||||
/*
|
||||
* Func: mmu_add_dma_range
|
||||
* Desc: Add a memrange for dma operations. This is special because we want to
|
||||
* initialize this memory as non-cacheable. We have a constraint that the DMA
|
||||
* buffer should be below 4GiB(32-bit only). So, we lookup a TYPE_NORMAL_MEM
|
||||
* from the lowest available addresses and align it to page size i.e. 64KiB.
|
||||
*/
|
||||
static struct mmu_memrange* mmu_add_dma_range(struct mmu_ranges *mmu_ranges)
|
||||
{
|
||||
int i = 0;
|
||||
struct mmu_memrange *r = &mmu_ranges->entries[0];
|
||||
|
||||
for (; i < mmu_ranges->used; i++) {
|
||||
|
||||
if ((r[i].type != TYPE_NORMAL_MEM) ||
|
||||
(r[i].size < DMA_DEFAULT_SIZE) ||
|
||||
(r[i].base >= MIN_64_BIT_ADDR))
|
||||
continue;
|
||||
|
||||
uint64_t base_addr;
|
||||
uint64_t range_end_addr = r[i].base + r[i].size;
|
||||
uint64_t size;
|
||||
uint64_t end_addr = range_end_addr;
|
||||
|
||||
/* Make sure we choose only 32-bit address range for DMA */
|
||||
if (end_addr > MIN_64_BIT_ADDR)
|
||||
end_addr = MIN_64_BIT_ADDR;
|
||||
|
||||
/*
|
||||
* We need to ensure that we do not step over payload regions or
|
||||
* the coreboot_table
|
||||
*/
|
||||
do {
|
||||
/*
|
||||
* If end_addr is aligned to GRANULE_SIZE,
|
||||
* then base_addr will be too.
|
||||
* (DMA_DEFAULT_SIZE is multiple of GRANULE_SIZE)
|
||||
*/
|
||||
assert((DMA_DEFAULT_SIZE % GRANULE_SIZE) == 0);
|
||||
end_addr = ALIGN_DOWN(end_addr, GRANULE_SIZE);
|
||||
|
||||
base_addr = end_addr - DMA_DEFAULT_SIZE;
|
||||
size = end_addr - base_addr;
|
||||
|
||||
if (base_addr < r[i].base)
|
||||
break;
|
||||
} while (mmu_is_dma_range_valid(base_addr, end_addr) == 0);
|
||||
|
||||
if (base_addr < r[i].base)
|
||||
continue;
|
||||
|
||||
if (r[i].size == size) {
|
||||
r[i].type = TYPE_DMA_MEM;
|
||||
return &r[i];
|
||||
}
|
||||
|
||||
if (end_addr != range_end_addr) {
|
||||
/* Add a new memrange since we split up one
|
||||
* range crossing the 4GiB boundary or doing an
|
||||
* ALIGN_DOWN on end_addr.
|
||||
*/
|
||||
r[i].size -= (range_end_addr - end_addr);
|
||||
if (mmu_add_memrange(mmu_ranges, end_addr,
|
||||
range_end_addr - end_addr,
|
||||
TYPE_NORMAL_MEM) == NULL)
|
||||
mmu_error();
|
||||
}
|
||||
|
||||
r[i].size -= size;
|
||||
|
||||
r = mmu_add_memrange(mmu_ranges, base_addr, size, TYPE_DMA_MEM);
|
||||
|
||||
if (r == NULL)
|
||||
mmu_error();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Should never reach here if everything went fine */
|
||||
printf("ARM64 ERROR: No DMA region allocated\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Func: mmu_extract_ranges
|
||||
* Desc: Assumption is that coreboot tables have memranges in sorted
|
||||
* order. So, if there is an opportunity to combine ranges, we do that as
|
||||
* well. Memranges are initialized for both CB_MEM_RAM and CB_MEM_TABLE as
|
||||
* TYPE_NORMAL_MEM.
|
||||
*/
|
||||
static void mmu_extract_ranges(struct memrange *cb_ranges,
|
||||
uint64_t ncb,
|
||||
struct mmu_ranges *mmu_ranges)
|
||||
{
|
||||
int i = 0;
|
||||
struct mmu_memrange *prev_range = NULL;
|
||||
|
||||
/* Extract memory ranges to be mapped */
|
||||
for (; i < ncb; i++) {
|
||||
switch (cb_ranges[i].type) {
|
||||
case CB_MEM_RAM:
|
||||
case CB_MEM_TABLE:
|
||||
if (prev_range && (prev_range->base + prev_range->size
|
||||
== cb_ranges[i].base)) {
|
||||
prev_range->size += cb_ranges[i].size;
|
||||
} else {
|
||||
prev_range = mmu_add_memrange(mmu_ranges,
|
||||
cb_ranges[i].base,
|
||||
cb_ranges[i].size,
|
||||
TYPE_NORMAL_MEM);
|
||||
if (prev_range == NULL)
|
||||
mmu_error();
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Func: mmu_init_ranges
|
||||
* Desc: Initialize mmu_memranges based on the memranges obtained from coreboot
|
||||
* tables. Also, initialize dma memrange and xlat_addr for ttb buffer.
|
||||
*/
|
||||
struct mmu_memrange *mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges,
|
||||
uint64_t ncb,
|
||||
struct mmu_ranges *mmu_ranges)
|
||||
{
|
||||
struct mmu_memrange *dma_range;
|
||||
|
||||
/* Extract ranges from memrange in lib_sysinfo */
|
||||
mmu_extract_ranges(cb_ranges, ncb, mmu_ranges);
|
||||
|
||||
/* Get a range for dma */
|
||||
dma_range = mmu_add_dma_range(mmu_ranges);
|
||||
|
||||
if (dma_range == NULL)
|
||||
mmu_error();
|
||||
|
||||
return dma_range;
|
||||
}
|
||||
|
||||
/*
|
||||
* Func: mmu_add_memrange
|
||||
* Desc: Adds a new memory range
|
||||
*/
|
||||
struct mmu_memrange* mmu_add_memrange(struct mmu_ranges *r, uint64_t base,
|
||||
uint64_t size, uint64_t type)
|
||||
{
|
||||
struct mmu_memrange *curr = NULL;
|
||||
int i = r->used;
|
||||
|
||||
if (i < ARRAY_SIZE(r->entries)) {
|
||||
curr = &r->entries[i];
|
||||
curr->base = base;
|
||||
curr->size = size;
|
||||
curr->type = type;
|
||||
|
||||
r->used = i + 1;
|
||||
}
|
||||
|
||||
return curr;
|
||||
}
|
||||
|
||||
/*
|
||||
* Func: mmu_presysinfo_memory_used
|
||||
* Desc: Initializes all the memory used for presysinfo page table
|
||||
* initialization and enabling of MMU. All these ranges are stored in
|
||||
* usedmem_ranges. usedmem_ranges plays an important role in selecting the dma
|
||||
* buffer as well since we check the dma buffer range against the used memory
|
||||
* ranges to prevent any overstepping.
|
||||
*/
|
||||
void mmu_presysinfo_memory_used(uint64_t base, uint64_t size)
|
||||
{
|
||||
uint64_t range_base;
|
||||
|
||||
range_base = ALIGN_DOWN(base, GRANULE_SIZE);
|
||||
|
||||
size += (base - range_base);
|
||||
size = ALIGN_UP(size, GRANULE_SIZE);
|
||||
|
||||
mmu_add_memrange(&usedmem_ranges, range_base, size, TYPE_NORMAL_MEM);
|
||||
}
|
||||
|
||||
void mmu_presysinfo_enable(void)
|
||||
{
|
||||
mmu_init(&usedmem_ranges);
|
||||
mmu_enable();
|
||||
}
|
||||
|
|
@ -107,9 +107,6 @@ void tlb_invalidate_all(void);
|
|||
* Generalized setup/init functions
|
||||
*/
|
||||
|
||||
/* mmu initialization (set page table address, set permissions, etc) */
|
||||
void mmu_init(void);
|
||||
|
||||
enum dcache_policy {
|
||||
DCACHE_OFF,
|
||||
DCACHE_WRITEBACK,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM64_MMU_H__
|
||||
#define __ARCH_ARM64_MMU_H__
|
||||
|
||||
#include <libpayload.h>
|
||||
|
||||
struct mmu_memrange {
|
||||
uint64_t base;
|
||||
uint64_t size;
|
||||
uint64_t type;
|
||||
};
|
||||
|
||||
struct mmu_ranges {
|
||||
struct mmu_memrange entries[SYSINFO_MAX_MEM_RANGES];
|
||||
size_t used;
|
||||
};
|
||||
|
||||
/*
|
||||
* Symbols taken from linker script
|
||||
* They mark the start and end of the region used by payload
|
||||
*/
|
||||
extern char _start[], _end[];
|
||||
|
||||
/* IMPORTANT!!!!!!!
|
||||
* Assumptions made:
|
||||
* Granule size is 64KiB
|
||||
* BITS per Virtual address is 33
|
||||
* All the calculations for tables L1,L2 and L3 are based on these assumptions
|
||||
* If these values are changed, recalculate the other macros as well
|
||||
*/
|
||||
|
||||
/* Memory attributes for mmap regions
|
||||
* These attributes act as tag values for memrange regions
|
||||
*/
|
||||
|
||||
#define TYPE_NORMAL_MEM 1
|
||||
#define TYPE_DEV_MEM 2
|
||||
#define TYPE_DMA_MEM 3
|
||||
|
||||
/* Descriptor attributes */
|
||||
|
||||
#define INVALID_DESC 0x0
|
||||
#define BLOCK_DESC 0x1
|
||||
#define TABLE_DESC 0x3
|
||||
#define PAGE_DESC 0x3
|
||||
|
||||
/* Block descriptor */
|
||||
#define BLOCK_NS (1 << 5)
|
||||
|
||||
#define BLOCK_AP_RW (0 << 7)
|
||||
#define BLOCK_AP_RO (1 << 7)
|
||||
|
||||
#define BLOCK_ACCESS (1 << 10)
|
||||
|
||||
/* XLAT Table Init Attributes */
|
||||
|
||||
#define VA_START 0x0
|
||||
/* If BITS_PER_VA or GRANULE_SIZE are changed, recalculate and change the
|
||||
macros following them */
|
||||
#define BITS_PER_VA 33
|
||||
/* Granule size of 64KB is being used */
|
||||
#define MIN_64_BIT_ADDR (1UL << 32)
|
||||
#define XLAT_TABLE_MASK ~(0xffffUL)
|
||||
#define GRANULE_SIZE_SHIFT 16
|
||||
#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT)
|
||||
#define GRANULE_SIZE_MASK ((1 << 16) - 1)
|
||||
|
||||
#define L1_ADDR_SHIFT 42
|
||||
#define L2_ADDR_SHIFT 29
|
||||
#define L3_ADDR_SHIFT 16
|
||||
|
||||
#define L1_ADDR_MASK (0UL << L1_ADDR_SHIFT)
|
||||
#define L2_ADDR_MASK (0xfUL << L2_ADDR_SHIFT)
|
||||
#define L3_ADDR_MASK (0x1fffUL << L3_ADDR_SHIFT)
|
||||
|
||||
/* Dependent on BITS_PER_VA and GRANULE_SIZE */
|
||||
#define INIT_LEVEL 2
|
||||
#define XLAT_MAX_LEVEL 3
|
||||
|
||||
/* Each entry in XLAT table is 8 bytes */
|
||||
#define XLAT_ENTRY_SHIFT 3
|
||||
#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SHIFT)
|
||||
|
||||
#define XLAT_TABLE_SHIFT GRANULE_SIZE_SHIFT
|
||||
#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SHIFT)
|
||||
|
||||
#define XLAT_NUM_ENTRIES_SHIFT (XLAT_TABLE_SHIFT - XLAT_ENTRY_SHIFT)
|
||||
#define XLAT_NUM_ENTRIES (1 << XLAT_NUM_ENTRIES_SHIFT)
|
||||
|
||||
#define L3_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT)
|
||||
#define L2_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT)
|
||||
#define L1_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT)
|
||||
|
||||
/* These macros give the size of the region addressed by each entry of a xlat
|
||||
table at any given level */
|
||||
#define L3_XLAT_SIZE (1 << L3_XLAT_SIZE_SHIFT)
|
||||
#define L2_XLAT_SIZE (1 << L2_XLAT_SIZE_SHIFT)
|
||||
#define L1_XLAT_SIZE (1 << L1_XLAT_SIZE_SHIFT)
|
||||
|
||||
/* Block indices required for MAIR */
|
||||
#define BLOCK_INDEX_MEM_DEV_NGNRNE 0
|
||||
#define BLOCK_INDEX_MEM_DEV_NGNRE 1
|
||||
#define BLOCK_INDEX_MEM_DEV_GRE 2
|
||||
#define BLOCK_INDEX_MEM_NORMAL_NC 3
|
||||
#define BLOCK_INDEX_MEM_NORMAL 4
|
||||
|
||||
#define BLOCK_INDEX_SHIFT 2
|
||||
|
||||
/* MAIR attributes */
|
||||
#define MAIR_ATTRIBUTES ((0x00 << (BLOCK_INDEX_MEM_DEV_NGNRNE*8)) | \
|
||||
(0x04 << (BLOCK_INDEX_MEM_DEV_NGNRE*8)) | \
|
||||
(0x0c << (BLOCK_INDEX_MEM_DEV_GRE*8)) | \
|
||||
(0x44 << (BLOCK_INDEX_MEM_NORMAL_NC*8)) | \
|
||||
(0xffUL << (BLOCK_INDEX_MEM_NORMAL*8)))
|
||||
|
||||
/* TCR attributes */
|
||||
#define TCR_TOSZ (64 - BITS_PER_VA)
|
||||
|
||||
#define TCR_IRGN0_SHIFT 8
|
||||
#define TCR_IRGN0_NM_NC (0x00 << TCR_IRGN0_SHIFT)
|
||||
#define TCR_IRGN0_NM_WBWAC (0x01 << TCR_IRGN0_SHIFT)
|
||||
#define TCR_IRGN0_NM_WTC (0x02 << TCR_IRGN0_SHIFT)
|
||||
#define TCR_IRGN0_NM_WBNWAC (0x03 << TCR_IRGN0_SHIFT)
|
||||
|
||||
#define TCR_ORGN0_SHIFT 10
|
||||
#define TCR_ORGN0_NM_NC (0x00 << TCR_ORGN0_SHIFT)
|
||||
#define TCR_ORGN0_NM_WBWAC (0x01 << TCR_ORGN0_SHIFT)
|
||||
#define TCR_ORGN0_NM_WTC (0x02 << TCR_ORGN0_SHIFT)
|
||||
#define TCR_ORGN0_NM_WBNWAC (0x03 << TCR_ORGN0_SHIFT)
|
||||
|
||||
#define TCR_SH0_SHIFT 12
|
||||
#define TCR_SH0_NC (0x0 << TCR_SH0_SHIFT)
|
||||
#define TCR_SH0_OS (0x2 << TCR_SH0_SHIFT)
|
||||
#define TCR_SH0_IS (0x3 << TCR_SH0_SHIFT)
|
||||
|
||||
#define TCR_TG0_SHIFT 14
|
||||
#define TCR_TG0_4KB (0x0 << TCR_TG0_SHIFT)
|
||||
#define TCR_TG0_64KB (0x1 << TCR_TG0_SHIFT)
|
||||
#define TCR_TG0_16KB (0x2 << TCR_TG0_SHIFT)
|
||||
|
||||
#define TCR_PS_SHIFT 16
|
||||
#define TCR_PS_4GB (0x0 << TCR_PS_SHIFT)
|
||||
#define TCR_PS_64GB (0x1 << TCR_PS_SHIFT)
|
||||
#define TCR_PS_1TB (0x2 << TCR_PS_SHIFT)
|
||||
#define TCR_PS_4TB (0x3 << TCR_PS_SHIFT)
|
||||
#define TCR_PS_16TB (0x4 << TCR_PS_SHIFT)
|
||||
#define TCR_PS_256TB (0x5 << TCR_PS_SHIFT)
|
||||
|
||||
#define TCR_TBI_SHIFT 20
|
||||
#define TCR_TBI_USED (0x0 << TCR_TBI_SHIFT)
|
||||
#define TCR_TBI_IGNORED (0x1 << TCR_TBI_SHIFT)
|
||||
|
||||
#define DMA_DEFAULT_SIZE (0x20 * GRANULE_SIZE)
|
||||
#define TTB_DEFAULT_SIZE 0x100000
|
||||
|
||||
/* Initialize the MMU TTB tables using the mmu_ranges */
|
||||
uint64_t mmu_init(struct mmu_ranges *mmu_ranges);
|
||||
|
||||
/* Enable the mmu based on previous mmu_init(). */
|
||||
void mmu_enable(void);
|
||||
|
||||
/* Disable mmu */
|
||||
void mmu_disable(void);
|
||||
|
||||
/*
|
||||
* Based on the memory ranges provided in coreboot tables,
|
||||
* initialize the mmu_memranges used for mmu initialization
|
||||
* cb_ranges -> Memory ranges present in cb tables
|
||||
* mmu_ranges -> mmu_memranges initialized by this function
|
||||
*/
|
||||
struct mmu_memrange* mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges,
|
||||
uint64_t ncb,
|
||||
struct mmu_ranges *mmu_ranges);
|
||||
|
||||
/* Add a new mmu_memrange */
|
||||
struct mmu_memrange* mmu_add_memrange(struct mmu_ranges *r, uint64_t base,
|
||||
uint64_t size, uint64_t type);
|
||||
|
||||
/*
|
||||
* Functions for handling the initialization of memory ranges and enabling mmu
|
||||
* before coreboot tables are parsed
|
||||
*/
|
||||
void mmu_presysinfo_memory_used(uint64_t base, uint64_t size);
|
||||
void mmu_presysinfo_enable(void);
|
||||
#endif // __ARCH_ARM64_MMU_H__
|
||||
Loading…
Reference in New Issue